Datasheet

REV. 0
–24–
ADSP-2188M
Parameter Min Max Unit
Clock Signals and Reset
Timing Requirements:
t
CKI
CLKIN Period 26.6 80 ns
t
CKIL
CLKIN Width Low 8 ns
t
CKIH
CLKIN Width High 8 ns
Switching Characteristics:
t
CKL
CLKOUT Width Low 0.5t
CK
– 2ns
t
CKH
CLKOUT Width High 0.5t
CK
– 2ns
t
CKOH
CLKIN High to CLKOUT High 0 13 ns
Control Signals Timing Requirements:
t
RSP
RESET Width Low 5t
CK
1
ns
t
MS
Mode Setup before RESET High 2 ns
t
MH
Mode Hold after RESET High 5 ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
t
CKOH
t
CKI
t
CKIH
t
CKIL
t
CKH
t
CKL
t
MH
t
MS
CLKIN
CLKOUT
PF(3:0)
*
RESET
*PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
t
RSP
Figure 21. Clock Signals