Datasheet

Rev. C | Page 44 of 48 | January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
LQFP PACKAGE PINOUT
The LQFP package pinout is shown in Table 29. Pin names in
bold text in the table replace the plain-text-named functions
when Mode C equals 1. A plus sign (+) separates two functions
when either function can be active for either major I/O mode.
Signals enclosed in brackets are state bits latched from the value
of the pin at the deassertion of RESET
. The multiplexed pins
DT1/FO, TFS1/IRQ1
, RFS1/IRQ0, and DR1/FI, are mode
selectable by setting Bit 10 (SPORT1 configure) of the System
Control Register. If Bit 10 = 1, these pins have serial port func-
tionality. If Bit 10 = 0, these pins are the external interrupt and
flag pins. This bit is set to 1 by default, upon reset.
Table 29. LQFP Pin Assignments
Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name
1A4/IAD3 26 IRQE
+ PF4 51 EBR 76 D16
2A5/IAD4 27 IRQL0
+ PF5 52 BR 77 D17
3GND28 GND 53 EBG
78 D18
4A6/IAD5 29 IRQL1
+ PF6 54 BG 79 D19
5A7/IAD6 30 IRQ2
+ PF7 55 D0/IAD13 80 GND
6A8/IAD7 31 DT0 56 D1/IAD14 81 D20
7A9/IAD8 32 TFS0 57 D2/IAD15 82 D21
8A10/IAD9 33 RFS0 58 D3/IACK
83 D22
9A11/IAD10 34 DR0 59 V
DDINT
84 D23
10 A12/IAD11 35 SCLK0 60 GND 85 FL2
11 A13/IAD12 36 V
DDEXT
61 D4/IS 86 FL1
12 GND 37 DT1/FO 62 D5/IAL 87 FL0
13 CLKIN 38 TFS1/IRQ1
63 D6/IRD 88 PF3 [Mode D
1
]
14 XTAL 39 RFS1/IRQ0
64 D7/IWR 89 PF2 [Mode C]
15 V
DDEXT
40 DR1/FI 65 D8 90 V
DDEXT
16 CLKOUT 41 GND 66 GND 91 PWD
17 GND 42 SCLK1 67 V
DDEXT
92 GND
18 V
DDINT
43 ERESET 68 D9 93 PF1 [Mode B]
19 WR
44 RESET 69 D10 94 PF0 [Mode A]
20 RD
45 EMS 70 D11 95 BGH
21 BMS 46 EE 71 GND 96 PWDACK
22 DMS
47 ECLK 72 D12 97 A0
23 PMS
48 ELOUT 73 D13 98 A1/IAD0
24 IOMS
49 ELIN 74 D14 99 A2/IAD1
25 CMS
50 EINT 75 D15 100 A3/IAD2
1
Mode D function available on ADSP-2187L only.