Datasheet

ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Rev. C | Page 27 of 48 | January 2008
Memory Write
Table 18. Memory Write
Parameter Min Max Unit
Switching Characteristics:
t
DW
Data Setup Before WR High
1
0.5t
CK
– 7 + w ns
t
DH
Data Hold After WR High 0.25t
CK
– 2 ns
t
WP
WR Pulse Width 0.5t
CK
– 5 + w ns
t
WDE
WR Low to Data Enabled 0 ns
t
ASW
A13–0, xMS Setup Before WR Low
2
0.25t
CK
– 6 ns
t
DDR
Data Disable Before WR or RD Low 0.25t
CK
– 7 ns
t
CWR
CLKOUT High to WR Low 0.25t
CK
– 5 0.25t
CK
+ 7 ns
t
AW
A13–0, xMS Setup Before WR Deasserted 0.75t
CK
– 9 + w ns
t
WRA
A13–0, xMS Hold After WR Deasserted 0.25t
CK
– 3 ns
t
WWR
WR High to RD or WR Low 0.5t
CK
– 5 ns
1
w = wait states × t
CK
.
2
xMS = PMS, DMS, CMS, IOMS, BMS.
Figure 20. Memory Write
CLKOUT
t
WP
t
AW
t
CWR
t
DH
t
WDE
t
DW
t
ASW
t
WWR
t
WRA
t
DDR
DMS, PMS,
BMS, CMS,
IOMS
RD
WR
1
ADDRESS LINE S FOR ACCESSES ARE:
2
DATA LINES FOR ACCESSES ARE:
BDMA: A13–0 (14 LSBs), D23–16 (8 MSBs) BDMA: D15–8
I/O SPACE: A10–0 I/O S PACE: D23–8
EXTERNAL PM AND DM: A13–0 EXTERNAL DM: D23–8
EXTERNAL P M: D23–0
ADDRESS LINES
1
DATA LINES
2