Datasheet

Rev. C | Page 24 of 48 | January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Interrupts and Flags
Table 15. Interrupts and Flags
Parameter Min Max Unit
Timing Requirements:
t
IFS
IRQx, FI, or PFx Setup Before CLKOUT Low
1, 2, 3, 4
0.25t
CK
+ 15 ns
t
IFH
IRQx, FI, or PFx Hold After CLKOUT High
1, 2, 3, 4
0.25t
CK
ns
Switching Characteristics:
t
FOH
Flag Output Hold After CLKOUT Low
5
0.5t
CK
– 5 ns
t
FOD
Flag Output Delay From CLKOUT Low
5
0.5t
CK
+ 4 ns
1
If IRQx and FI inputs meet t
IFS
and t
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the
following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-218x DSP Hardware Reference for further information on
interrupt servicing.)
2
Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag Outputs = PFx, FL0, FL1, FL2, FO.
Figure 17. Interrupts and Flags
t
FOD
t
FOH
t
IFH
t
IFS
CLKOUT
FLAG
OUTPUTS
IRQx
FI
PFx