Datasheet

ManualsBrandsANALOG DEVICES ManualsMicrocontrollers, Microprocessors & QuartzesDigital signal processor (DSP) LQFP 100 (14x14) 3.3 V 52 MHz

ICE-Port is a trademark of Analog Devices, Inc.

DSP Microcomputer

ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L

Rev. C

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PERFORMANCE FEATURES

Up to 19 ns instruction cycle time, 52 MIPS sustained

performance

Single-cycle instruction execution

Single-cycle context switch

3-bus architecture allows dual operand fetches in every

instruction cycle

Multifunction instructions

Power-down mode featuring low CMOS standby power dissi-

pation with 400 CLKIN cycle recovery from power-down

condition

Low power dissipation in idle mode

INTEGRATION FEATURES

ADSP-2100 family code compatible (easy to use algebraic

syntax), with instruction set extensions

Up to 160K bytes of on-chip RAM, configured

Up to 32K words program memory RAM

Up to 32K words data memory RAM

Dual-purpose program memory for both instruction and

data storage

Independent ALU, multiplier/accumulator, and barrel shifter

computational units

2 independent data address generators

Powerful program sequencer provides zero overhead loop-

ing conditional instruction execution

Programmable 16-bit interval timer with prescaler

100-lead LQFP and 144-ball BGA

SYSTEM INTERFACE FEATURES

16-bit internal DMA port for high-speed access to on-chip

memory (mode selectable)

4M-byte memory interface for storage of data tables and pro-

gram overlays (mode selectable)

8-bit DMA to byte memory for transparent program and data

memory transfers (mode selectable)

Programmable memory strobe and separate I/O memory

space permits “glueless” system design

Programmable wait state generation

2 double-buffered serial ports with companding hardware

and automatic data buffering

Automatic booting of on-chip program memory from byte-

wide external memory, for example, EPROM, or through

internal DMA Port

6 external interrupts

13 programmable flag pins provide flexible system signaling

UART emulation through software SPORT reconfiguration

ICE-Port emulator interface supports debugging in final

systems

Figure 1. Functional Block Diagram

ARITHMETIC UNITS

SHIFTERMAC

ALU

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

POWER-DOWN

CONTROL

MEMORY

PROGRAM

MEMORY

UP TO

32K ⴛ 24-BIT

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

SPORT0

SERIAL PORTS

SPORT1

PROGRAMMABLE

I/O

AND

FLAGS

TIMER

HOST MODE

EXTERNAL

DATA

BUS

INTERNAL

DMA

PORT

DAG1

DATA ADDRESS

GENERATORS

DAG2

PROGRAM

SEQUENCER

ADSP-2100 BASE

ARCHITECTURE

DATA

MEMORY

UP TO

32K ⴛ 16-BIT

FUL L MEMORY MODE

Summary of content (48 pages)

PAGE 1
DSP Microcomputer ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L PERFORMANCE FEATURES SYSTEM INTERFACE FEATURES Up to 19 ns instruction cycle time, 52 MIPS sustained performance Single-cycle instruction execution Single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle Multifunction instructions Power-down mode featuring low CMOS standby power dissipation with 400 CLKIN cycle recovery from power-down condition Low power dissipation in idle mode 16-bit internal DM
PAGE 2
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L TABLE OF CONTENTS Performance Features ............................................... 1 Specifications ........................................................ 21 Integration Features ................................................. 1 Operating Conditions ........................................... 21 System Interface Features ........................................... 1 Electrical Characteristics .......................................
PAGE 3
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L GENERAL DESCRIPTION The ADSP-218xL series consists of four single chip microcomputers optimized for digital signal processing applications. The functional block diagram for the ADSP-218xL series members appears in Figure 1 on Page 1. All series members are pin-compatible and are differentiated solely by the amount of on-chip SRAM. This feature, combined with ADSP-21xx code compatibility, provides a great deal of flexibility in the design decision.
PAGE 4
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permitting ADSP-218xL series members to fetch two operands in a single cycle, one from program memory and one from data memory.
PAGE 5
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Table 2. Modes of Operation 1 2 Mode D1 X Mode C 0 Mode B 0 Mode A 0 X 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 1 Booting Method BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Full Memory Mode.2 No automatic boot operations occur. Program execution starts at external memory location 0.
PAGE 6
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Individual interrupt requests are logically AND’ed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable. ADSP-218xL series members mask all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers.
PAGE 7
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). power-down state. For additional information, refer to the ADSP-218x DSP Hardware Reference, for detailed information on this power-down feature. SYSTEM INTERFACE If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate.
PAGE 8
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L sequence is performed. The first instruction is fetched from onchip program memory location 0x0000 once boot loading completes. 1M⍀ MEMORY ARCHITECTURE XTAL CLKIN The ADSP-218xL series provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O. Refer to Figure 4 through Figure 7 for PM and DM memory allocations in the ADSP-218xL series. CLKOUT DSP Figure 3.
PAGE 9
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L PROGRAM MEMORY MODEB = 1 0x3FFF PROGRAM MEMORY MODEB = 0 0x3FFF 0x3FFF PM OVERLAY 1,2 (EXTERNAL PM) RESERVED DATA MEMORY 32 MEMORY-MAPPED CONTROL REGISTERS 0x3FE0 0x3FDF PM OVERLAY 0 (INTERNAL PM) 0x2000 0x1FFF 0x2000 0x1FFF EXTERNAL PM INTERNAL DM 0x2000 0x1FFF DM OVERLAY 1,2 (EXTERNAL DM) INTERNAL PM DM OVERLAY 0 (INTERNAL DM) 0x0000 0x0000 0x0000 Figure 5.
PAGE 10
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Table 4.
PAGE 11
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L See Figure 9 and Figure 10 for illustration of the programmable flag and composite control register and the system control register.
PAGE 12
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L create a destination word, it is transferred to or from on-chip memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses. The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations.
PAGE 13
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Note: In Full Memory Mode, all locations of 4M-byte memory space are directly addressable. In Host Memory Mode, only address pin A0 is available, requiring additional external logic to provide address information for the byte.
PAGE 14
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L INSTRUCTION SET DESCRIPTION • Fill and dump memory The ADSP-218xL series assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor’s unique architecture, offers the following benefits: • Source level debugging • The algebraic syntax eliminates the need to remember cryptic assembler mnemonics.
PAGE 15
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L • Complete assembly and disassembly of instructions The EZ-ICE connects to the target system via a ribbon cable and a 14-pin female plug. The female plug is plugged onto the 14pin connector (a pin strip header) on the target board. • C source-level debugging Designing an EZ-ICE-Compatible System Target Board Connector for EZ-ICE Probe ADSP-218xL series members have on-chip emulation support and an ICE-Port, a special set of pins that interface to the EZ-ICE.
PAGE 16
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These resistors may be removed when the EZ-ICE is not being used. Target System Interface Signals When the EZ-ICE board is installed, the performance on some system signals changes.
PAGE 17
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L PIN DESCRIPTIONS ADSP-218xL series members are available in a 100-lead LQFP package and a 144-ball BGA package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution.
PAGE 18
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Table 9. Common-Mode Pins (Continued) Pin Name VDDINT VDDEXT GND EZ-Port No. of Pins 4 7 20 9 I/O I I I I/O Function Internal VDD (3.3 V) Power (BGA) External VDD (3.3 V) Power (BGA) Ground (BGA) For Emulation Use 1 Interrupt/Flag pins retain both functions concurrently.
PAGE 19
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L TERMINATING UNUSED PINS Table 12 shows the recommendations for terminating unused pins. Table 12.
PAGE 20
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Table 12.
PAGE 21
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L SPECIFICATIONS OPERATING CONDITIONS Parameter1 Min 3.0 0 VDD TAMB 1 K Grade (Commercial) Max 3.6 +70 Min 3.0 –40 B Grade (Industrial) Max 3.6 +85 Unit V °C Specifications subject to change without notice.
PAGE 22
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L ABSOLUTE MAXIMUM RATINGS ESD SENSITIVITY Stresses greater than those listed below may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PAGE 23
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Clock Signals and Reset Table 14.
PAGE 24
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Interrupts and Flags Table 15. Interrupts and Flags Parameter Timing Requirements: IRQx, FI, or PFx Setup Before CLKOUT Low1, 2, 3, 4 tIFS tIFH IRQx, FI, or PFx Hold After CLKOUT High1, 2, 3, 4 Switching Characteristics: tFOH Flag Output Hold After CLKOUT Low5 tFOD Flag Output Delay From CLKOUT Low5 Min Max 0.25tCK + 15 0.25tCK ns ns 0.5tCK – 5 ns ns 0.
PAGE 25
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Bus Request–Bus Grant Table 16. Bus Request—Bus Grant Parameter Timing Requirements: BR Hold After CLKOUT High1 tBH tBS BR Setup Before CLKOUT Low1 Switching Characteristics: tSD CLKOUT High to xMS, RD, WR Disable2 tSDB xMS, RD, WR Disable to BG Low tSE BG High to xMS, RD, WR Enable xMS, RD, WR Enable to CLKOUT High3 tSEC tSDBH xMS, RD, WR Disable to BGH Low4 tSEH BGH High to xMS, RD, WR Enable4 Min Max 0.25tCK + 2 0.25tCK + 17 ns ns 0.25tCK + 10 0 0 0.
PAGE 26
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Memory Read Table 17. Memory Read Parameter Timing Requirements: RD Low to Data Valid1 tRDD tAA A13–0, xMS to Data Valid2 tRDH Data Hold from RD High3 Switching Characteristics: tRP RD Pulse Width tCRD CLKOUT High to RD Low A13–0, xMS Setup Before RD Low tASR tRDA A13–0, xMS Hold After RD Deasserted tRWR RD High to RD or WR Low Min Unit 0.5tCK – 9 + w 0.75tCK – 12.5 + w ns ns ns 1 0.5tCK – 5 + w 0.25tCK – 5 0.25tCK – 6 0.25tCK – 3 0.
PAGE 27
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Memory Write Table 18. Memory Write Parameter Switching Characteristics: Data Setup Before WR High1 tDW tDH Data Hold After WR High tWP WR Pulse Width tWDE WR Low to Data Enabled tASW A13–0, xMS Setup Before WR Low2 tDDR Data Disable Before WR or RD Low CLKOUT High to WR Low tCWR tAW A13–0, xMS Setup Before WR Deasserted tWRA A13–0, xMS Hold After WR Deasserted tWWR WR High to RD or WR Low 1 2 Min Max 0.5tCK– 7 + w 0.25tCK – 2 0.5tCK – 5 + w 0 0.25tCK – 6 0.
PAGE 28
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Serial Ports Table 19.
PAGE 29
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L CLKOUT t CC tCC tS C K SCLK tS CP t SC S DR TFSIN RFSIN tSC H tSC P tRD tR H RFSO UT TFSO UT tS C DD t SC D V tSC D H tS CD E DT tTD E t TD V TFSO UT A LTER N A TE FRA M E M OD E tR DV RFS OU T MU LTIC H A NN E L M ODE , FR A ME DE LA Y 0 ( MFD = 0 ) TFSIN tTD E tTD V ALTE R NA TE FR A ME MO DE tR DV RFSIN MU LTIC H A NN E L M ODE , FR A ME DE LA Y 0 ( MFD = 0 ) Figure 21. Serial Ports Rev.
PAGE 30
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L IDMA Address Latch Table 20. IDMA Address Latch Parameter Timing Requirements: Duration of Address Latch1, 2 tIALP tIASU IAD15–0 Address Setup Before Address Latch End2 tIAH IAD15–0 Address Hold After Address Latch End2, 3 tIKA IACK Low Before Start of Address Latch2, 4 tIALS Start of Write or Read After Address Latch End2, 4 tIALD Address Latch Start After Address Latch End1, 2 Min 10 5 3 0 3 2 1 Start of Address Latch = IS Low and IAL High.
PAGE 31
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L IDMA Write, Short Write Cycle Table 21. IDMA Write, Short Write Cycle Parameter Timing Requirements: IACK Low Before Start of Write1 tIKW tIWP Duration of Write1, 2 tIDSU IAD15–0 Data Setup Before End of Write2, 3, 4 tIDH IAD15–0 Data Hold After End of Write2, 3, 4 Switching Characteristic: tIKHW Start of Write to IACK High5 Min 0 15 5 2 Start of Write = IS Low and IWR Low. End of Write = IS High or IWR High.
PAGE 32
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L IDMA Write, Long Write Cycle Table 22. IDMA Write, Long Write Cycle Parameter Timing Requirements: IACK Low Before Start of Write1 tIKW tIKSU IAD15–0 Data Setup Before End of Write2, 3, 4 tIKH IAD15–0 Data Hold After End of Write2, 3, 4 Switching Characteristics: tIKLW Start of Write to IACK Low4 tIKHW Start of Write to IACK High5 Min Max 0 0.5tCK + 10 2 ns ns ns 1.5tCK 17 1 Start of Write = IS Low and IWR Low.
PAGE 33
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L IDMA Read, Long Read Cycle Table 23.
PAGE 34
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L IDMA Read, Short Read Cycle Table 24.
PAGE 35
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L IDMA Read, Short Read Cycle in Short Read Only Mode Table 25.
PAGE 36
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L POWER SUPPLY CURRENT Table 26. Power Supply Current1 Parameter ADSP-2184L IDD Supply Current (Idle)2 IDD Supply Current (Dynamic)3 ADSP-2185L IDD Supply Current (Idle)2 IDD Supply Current (Dynamic)3 ADSP-2186L IDD Supply Current (Idle)2 IDD Supply Current (Dynamic)3 ADSP-2187L IDD Supply Current (Idle)2 IDD Supply Current (Dynamic)3 Test Conditions Min @ VDD = 3.3 V4 @ VDD = 3.3, TAMB = 25°C, tCK = 25 ns4 @ VDD = 3.
PAGE 37
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L POWER DISSIPATION Assumptions: • External data memory is accessed every cycle with 50% of the address pins switching. To determine total power dissipation in a specific application, the following equation should be applied for each output: C ⴛ VDD2 ⴛ f • External data memory writes occur every other cycle with 50% of the data pins switching. where: • Each address and data pin has a 10 pF total load at the pin. C is load capacitance.
PAGE 38
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L POWER, INTERNAL1, 2, 3 170 169mW V DDINT = 3.6V 150 140 1 26mW 130 139 mW V DDINT = 3.3V 120 110 10 2mW V DDIN T = 3.0V 11 3mW 100 90 19 7mW 210 POWER (P IN T) – mW POWER (P IN T) – mW 160 POWER, INTERNAL 1 , 2 , 3 230 190 VD D IN T = 3.6V 161m W 170 VD D INT = 3.3V 150 13 0mW 128m W 130 VD D INT = 3.0V 110 104m W 90 83mW 80 32 30 84m W 70 34 36 38 40 50 42 30 35 1/tCK – MHz 34 V DDINT = 3.6V 32 27mW 28 VDDINT = 3.
PAGE 39
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L POWER, INTERNAL 1, 2, 3 170 210 169mW VDD INT = 3.6V 150 140 126mW 139 mW V DDINT = 3.3V 130 POWER (P IN T) – mW POWER (P IN T) – mW 160 120 110 10 2mW V DDINT = 3.0V 1 13mW 100 90 POWER, INTERNAL 1, 2, 3 230 170 VDDINT = 3.3V 150 130 110 70 50 30 VDDINT = 3.0V 13 2mW 112.2mW 32 34 36 38 40 42 87mW 35 30 40 POWER, IDLE1, 2, 4 38 45 50 55 1/ tCK – MHz 1/tCK – MHz POWER, IDLE1, 2, 4 36 V DDINT = 3.
PAGE 40
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L OUTPUT DRIVE CURRENTS Figure 32 through Figure 35 show typical I-V characteristics for the output drivers on the ADSP-218xL processors. The curves represent the current drive capability of the output drivers as a function of output voltage. 80 80 VDDEXT = 3.3V @ +25ⴗC VDDEXT = 3.3V @ +25ⴗC VDDEXT = 3.6V @ –40 ⴗC 60 VDDEXT = 3.6V @ –40 ⴗC 60 VOH SOURCE CURRENT – mA SOURCE CURRENT – mA VOH 40 20 VDDEXT = 3.0V @ +85ⴗC 0 VDDEXT = 3.
PAGE 41
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L POWER-DOWN CURRENT Figure 36 through Figure 39 show the typical power-down supply current. Note that these graphs reflect ADSP-218xL operation in lowest power mode. (See the “System Interface” chapter of the ADSP-218x DSP Hardware Reference for details). Current reflects device operating with no input loads. 10000 VDD = 3.6V 1000 VDD = 3.3V 100 10 CURRENT (LOG SCALE) – µA CURRENT (LOG SCALE) – µA 10000 VDD = 3.
PAGE 42
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L CAPACITIVE LOADING – ADSP-2184L, ADSP-2186L CAPACITIVE LOADING – ADSP-2185L, ADSP-2187L Figure 40 and Figure 41 show the capacitive loading characteristics of the ADSP-2184L and ADSP-2186L. Figure 42 and Figure 43 show the capacitive loading characteristics of the ADSP-2185L and ADSP-2187L. 18 25 T = 85ⴗC VDD = 3.0V T = 85ⴗC VDD = 3.0V 15 RISE TIME (0.4V–2.4V) – ns RISE TIME (0.4V–2.
PAGE 43
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L TEST CONDITIONS REFERENCE SIGNAL Figure 44 shows voltage reference levels for all ac measurements (except output disable/enable). tMEASURED tENA tDIS VOH (MEASURED) INPUT OR OUTPUT 1.5V VOH (MEASURED) VOH (MEASURED) – 0.5V 2.0V VOL (MEASURED) + 0.5V 1.0V OUTPUT 1.5V VOL (MEASURED) Figure 44. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) OUTPUT STARTS DRIVING OUTPUT STOPS DRIVING HIGH-IMPEDANCE STATE.
PAGE 44
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L LQFP PACKAGE PINOUT The LQFP package pinout is shown in Table 29. Pin names in bold text in the table replace the plain-text-named functions when Mode C equals 1. A plus sign (+) separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets are state bits latched from the value of the pin at the deassertion of RESET.
PAGE 45
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L BGA PACKAGE PINOUT The BGA package pinout is shown in Table 30. Pin names in bold text in the table replace the plain text named functions when Mode C equals 1. A plus sign (+) separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets are state bits latched from the value of the pin at the deassertion of RESET.
PAGE 46
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L OUTLINE DIMENSIONS A1 BALL CORNER 10.10 10.00 SQ 9.90 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M BALL A1 PAD CORNER 8.80 BSC SQ 0.80 BSC TOP VIEW BOTTOM VIEW 0.60 REF DETAIL A 1.40 1.34 1.19 1.11 1.01 0.91 DETAIL A 0.33 NOM 0.28 MIN COPLANARITY 0.12 *0.50 0.45 0.40 BALL DIAMETER SEATING PLANE *COMPLIANT TO JEDEC STANDARDS MO-205-AC WITH THE EXCEPTION TO BALL DIAMETER. Figure 47. 144-Ball BGA [CSP_BGA] (BC-144-6) 16.00 BSC SQ 1.60 MAX 0.
PAGE 47
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L SURFACE MOUNT DESIGN Table 31 is provided as an aid to PCB design to accommodate BGA style surface mount packages. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 31. BGA Data for Use with Surface Mount Design Package 144-Ball BGA (BC-144-6) Ball Attach Type Solder Mask Defined Solder Mask Opening 0.40 mm diameter Ball Pad Size 0.
PAGE 48
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00192-0-1/08(C) Rev.