Datasheet

ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Rev. C | Page 35 of 48 | January 2008
IDMA Read, Short Read Cycle in Short Read Only Mode
Table 25. IDMA Read, Short Read Cycle in Short Read Only Mode
1
Parameter
2
Min Max Unit
Timing Requirements:
t
IKR
IACK Low Before Start of Read
3
0ns
t
IRP
Duration of Read
4
10 ns
Switching Characteristics:
t
IKHR
IACK High After Start of Read
3
10 ns
t
IKDH
IAD15–0 Previous Data Hold After End of Read
4
0ns
t
IKDD
IAD15–0 Previous Data Disabled After End of Read
4
10 ns
t
IRDE
IAD15–0 Previous Data Enabled After Start of Read 0 ns
t
IRDV
IAD15–0 Previous Data Valid After Start of Read 10 ns
1
Applies to the ADSP-2187L only.
2
Short Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register or by
an external host writing to the register. Disabled by default.
3
Start of Read = IS Low and IRD Low. Previous data remains until end of read.
4
End of Read = IS High or IRD High.
Figure 27. IDMA Read, Short Read Cycle in Short Read Only Mode
t
IR P
t
IKR
PREVIOUS
DATA
t
IKHR
t
IR D V
t
IKDD
t
IR D E
t
IK D H
IAD15–0
IA C K
IS
IR D
LEGEND:
IM P LIE S TH A T IS AND IRD CAN BE
HELD INDEFINITELY BY HOST