Datasheet

Rev. C | Page 34 of 48 | January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
IDMA Read, Short Read Cycle
Table 24. IDMA Read, Short Read Cycle
Parameter
1, 2
Min Max Unit
Timing Requirements:
t
IKR
IACK Low Before Start of Read
3
0ns
t
IRP1
Duration of Read (DM/PM1)
4, 5
15 ns
t
IRP2
Duration of Read (PM2)
6, 7
15 ns
Switching Characteristics:
t
IKHR
IACK High After Start of Read
3
15 ns
t
IKDH
IAD15–0 Data Hold After End of Read
8
0ns
t
IKDD
IAD15–0 Data Disabled After End of Read
8
10 ns
t
IRDE
IAD15–0 Previous Data Enabled After Start of Read 0 ns
t
IRDV
IAD15–0 Previous Data Valid After Start of Read 15 ns
1
Short Read Only must be disabled in the IDMA overlay memory mapped register. This mode is disabled by clearing (=0) Bit 14 of the IDMA overlay register, and is disabled
by default upon reset.
2
Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.
3
Start of Read = IS Low and IRD Low.
4
DM Read or first half of PM Read.
5
For the ADSP-2186L, this specification also has a max value of 2t
CK
– 5.
6
Second half of PM Read.
7
For the ADSP-2186L, this specification also has a max value of t
CK
– 5 max.
8
End of Read = IS High or IRD High.
Figure 26. IDMA Read, Short Read Cycle
t
IRPx
t
IKR
PREVIOUS
DATA
t
IKHR
t
IRDV
t
IKDD
t
IRDE
t
IKDH
IAD15–0
IACK
IS
IRD