Datasheet

ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Rev. C | Page 25 of 48 | January 2008
Bus Request–Bus Grant
Table 16. Bus Request—Bus Grant
Parameter Min Max Unit
Timing Requirements:
t
BH
BR Hold After CLKOUT High
1
0.25t
CK
+ 2 ns
t
BS
BR Setup Before CLKOUT Low
1
0.25t
CK
+ 17 ns
Switching Characteristics:
t
SD
CLKOUT High to xMS, RD, WR Disable
2
0.25t
CK
+ 10 ns
t
SDB
xMS, RD, WR Disable to BG Low 0 ns
t
SE
BG High to xMS, RD, WR Enable 0 ns
t
SEC
xMS, RD, WR Enable to CLKOUT High
3
0.25t
CK
– 7 ns
t
SDBH
xMS, RD, WR Disable to BGH Low
4
0ns
t
SEH
BGH High to xMS, RD, WR Enable
4
0ns
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the
following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2
xMS = PMS, DMS, CMS, IOMS, BMS.
3
For the ADSP-2187L, this specification is 0.25t
CK
– 4 ns min.
4
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
Figure 18. Bus Request—Bus Grant
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
SDBH
t
SEH
t
BS
BR
t
BH
CLKOUT
PMS, DMS
BMS, RD
CMS, WR,
IOMS
BG
BGH