Datasheet

ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Rev. C | Page 23 of 48 | January 2008
Clock Signals and Reset
Table 14. Clock Signals and Reset
ADSP-2184L, ADSP-2186L ADSP-2185L, ADSP-2187L
Parameter Min Max Min Max Unit
Timing Requirements:
t
CKI
CLKIN Period 50 150 38 100 ns
t
CKIL
CLKIN Width Low 20 15 ns
t
CKIH
CLKIN Width High 20 15 ns
Switching Characteristics:
t
CKL
CLKOUT Width Low 0.5t
CK
– 7 0.5t
CK
– 7 ns
t
CKH
CLKOUT Width High 0.5t
CK
– 7 0.5t
CK
– 7 ns
t
CKOH
CLKIN High to CLKOUT High 0 20 0 20 ns
Control Signals Timing Requirements:
t
RSP
RESET Width Low
1
5t
CK
5t
CK
ns
t
MS
Mode Setup Before RESET High 2 2 ns
t
MH
Mode Hold After RESET High 5 5 ns
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal oscillator
start-up time).
Figure 16. Clock Signals and Reset
t
CKOH
t
CKI
t
CKIH
t
CKIL
t
CKH
t
CKL
t
MH
t
MS
CLKIN
CLKOUT
MODE A D
RESET
t
RSP