Datasheet

ADSP-2183
–14– REV. C
Parameter Min Max Unit
Clock Signals and Reset
Timing Requirements:
t
CKI
CLKIN Period 38 100 ns
t
CKIL
CLKIN Width Low 15 ns
t
CKIH
CLKIN Width High 15 ns
Switching Characteristics:
t
CKL
CLKOUT Width Low 0.5t
CK
– 7 ns
t
CKH
CLKOUT Width High 0.5t
CK
– 7 ns
t
CKOH
CLKIN High to CLKOUT High 0 20 ns
Control Signals
Timing Requirement:
t
RSP
RESET Width Low 5t
CK
1
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
CLKIN
CLKOUT
t
CKIL
t
CKOH
t
CKH
t
CKL
t
CKIH
t
CKI
Figure 8. Clock Signals
Parameter Min Max Unit
Interrupts and Flag
Timing Requirements:
t
IFS
IRQx, FI, or PFx Setup before CLKOUT Low
1, 2, 3, 4
0.25t
CK
+ 15 ns
t
IFH
IRQx, FI, or PFx Hold after CLKOUT High
1, 2, 3, 4
0.25t
CK
ns
Switching Characteristics:
t
FOH
Flag Output Hold after CLKOUT Low
5
0.5t
CK
– 7 ns
t
FOD
Flag Output Delay from CLKOUT Low
5
0.5t
CK
+ 6 ns
NOTES
1
If IRQx and FI inputs meet t
IFS
and t
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0 , IRQL1, IRQE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.
t
FOD
t
FOH
t
IFS
CLKOUT
FLAG
OUTPUTS
IRQx
FI
PFx
t
IFH
Figure 9. Interrupts and Flags