Datasheet

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Rev. B | Page 33 of 68 | March 2013
AMI Read
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD
,
AMI_WR
, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 32. AMI Read
Parameter Min Max Unit
Timing Requirements
t
DAD
1, 2, 3
Address Selects Delay to Data Valid W + t
SDCLK
–5.4 ns
t
DRLD
1, 3
AMI_RD Low to Data Valid W – 3.2 ns
t
SDS
Data Setup to AMI_RD High 2.5 ns
t
HDRH
4, 5
Data Hold from AMI_RD High 0 ns
t
DAAK
2, 6
AMI_ACK Delay from Address, Selects t
SDCLK
–9.5 + W ns
t
DSAK
4
AMI_ACK Delay from AMI_RD Low W – 7 ns
Switching Characteristics
t
DRHA
Address Selects Hold After AMI_RD High RHC + 0.20 ns
t
DARL
2
Address Selects to AMI_RD Low t
SDCLK
– 3.8 ns
t
RW
AMI_RD Pulse Width W – 1.4 ns
t
RWR
AMI_RD High to AMI_RD Low HI + t
SDCLK
– 1 ns
W = (number of wait states specified in AMICTLx register) × t
SDCLK
.
RHC = (number of Read Hold Cycles specified in AMICTLx register) × t
SDCLK
Where PREDIS = 0
HI = RHC: Read to Read from same bank
HI = RHC + IC: Read to Read from different bank
HI = RHC + Max (IC, (4 × t
SDCLK
)): Read to Write from same or different bank
Where PREDIS = 1
HI = RHC + Max (IC, (4 × t
SDCLK
)): Read to Write from same or different bank
HI = RHC + (3 × t
SDCLK
): Read to Read from same bank
HI = RHC + Max (IC, (3 × t
SDCLK
): Read to Read from different bank
IC = (number of idle cycles specified in AMICTLx register) × t
SDCLK
H = (number of hold cycles specified in AMICTLx register) × tSDCLK
1
Data delay/setup: System must meet t
DAD
, t
DRLD
, or t
SDS.
2
The falling edge of MSx, is referenced.
3
The maximum limit of timing requirement values for t
DAD
and t
DRLD
parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not
used.
4
Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.
5
Data hold: User must meet t
HDRH
in asynchronous access mode. See Test Conditions on Page 55 for the calculation of hold times given capacitive and dc loads.
6
AMI_ACK delay/setup: User must meet t
DAAK
, or t
DSAK
, for deassertion of AMI_ACK (low).