Datasheet

Rev. B | Page 46 of 68 | March 2013
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Figure 31 shows the default I
2
S-justified mode. The frame sync
is low for the left channel and HI for the right channel. Data is
valid on the rising edge of serial clock. The MSB is left-justified
to the frame sync transition but with a delay.
Figure 32 shows the left-justified mode. The frame sync is high
for the left channel and low for the right channel. Data is valid
on the rising edge of serial clock. The MSB is left-justified to the
frame sync transition with no delay.
Table 45. S/PDIF Transmitter I
2
S Mode
Parameter Nominal Unit
Timing Requirement
t
I2SD
Frame Sync to MSB Delay in I
2
S Mode 1 SCLK
Figure 31. I
2
S-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
t
I2SD
Table 46. S/PDIF Transmitter Left-Justified Mode
Parameter Nominal Unit
Timing Requirement
t
LJD
Frame Sync to MSB Delay in Left-Justified Mode 0 SCLK
Figure 32. Left-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
t
LJD