Datasheet

Rev. C | Page 64 of 76 | July 2013
ADSP-21477/ADSP-21478/ADSP-21479
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
For information on the UART port receive and transmit opera-
tions, see the ADSP-214xx SHARC Hardware Reference Manual.
2-Wire Interface (TWI)—Receive and Transmit Timing
For information on the TWI receive and transmit operations,
see the ADSP-214xx SHARC Hardware Reference Manual.
JTAG Test Access Port and Emulation
Table 55. JTAG Test Access Port and Emulation
88-Lead LFCSP Package All Other Packages
Unit
Parameter Min Max Min Max
Timing Requirements
t
TCK
TCK Period 20 20 ns
t
STAP
TDI, TMS Setup Before TCK High 5 5 ns
t
HTAP
TDI, TMS Hold After TCK High 6 6 ns
t
SSYS
1
1
System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG1–0, DAI_Px, DPI_Px, FLAG3–0, MLBCLK, MLBDAT, MLBSIG, SR_SCLK, SR_CLR, SR_SDI, and
SR_LAT.
System Inputs Setup Before TCK High 7 7 ns
t
HSYS
1
System Inputs Hold After TCK High 18 18 ns
t
TRSTW
TRST Pulse Width 4 × t
CK
4 × t
CK
ns
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 11.5 10.5 ns
t
DSYS
2
2
System Outputs = DAI_Px, DPI_Px, ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK, MLBDAT, MLBSIG, MLBDO,
MLBSO, SR_SDO, SR_LDO, and EMU.
System Outputs Delay After TCK Low t
CK
÷ 2 + 7 t
CK
÷ 2 + 7 ns
Figure 46. IEEE 1149.1 JTAG Test Access Port
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS