Datasheet

ADSP-21477/ADSP-21478/ADSP-21479
Rev. C | Page 61 of 76 | July 2013
Shift Register
Table 54. Shift Register
Parameter Min Max Unit
Timing Requirements
t
SSDI
SR_SDI Setup Before SR_SCLK Rising Edge 7 ns
t
HSDI
SR_SDI Hold After SR_SCLK Rising Edge 2 ns
t
SSDIDAI
1
DAI_P08–01 (SR_SDI) Setup Before DAI_P08–01 (SR_SCLK) Rising Edge 7 ns
t
HSDIDAI
1
DAI_P08–01 (SR_SDI) Hold After DAI_P08–01 (SR_SCLK) Rising Edge 2 ns
t
SSCK2LCK
2
SR_SCLK to SR_LAT Setup 2 ns
t
SSCK2LCKDAI
1, 2
DAI_P08–01 (SR_SCLK) to DAI_P08–01 (SR_LAT) Setup 2 ns
t
CLRREM2SCK
Removal Time SR_CLR to SR_SCLK 3 × t
PCLK
– 5 ns
t
CLRREM2LCK
Removal Time SR_CLR to SR_LAT 2 × t
PCLK
– 5 ns
t
CLRW
SR_CLR Pulse Width 4 × t
PCLK
– 5 ns
t
SCKW
SR_SCLK Clock Pulse Width 2 × t
PCLK
– 2 ns
t
LCKW
SR_LAT Clock Pulse Width 2 × t
PCLK
– 5 ns
f
MAX
Maximum Clock Frequency SR_SCLK or SR_LAT f
PCLK
 4MHz
Switching Characteristics ns
t
DSDO1
3
SR_SDO Hold After SR_SCLK Rising Edge 3 ns
t
DSDO2
3
SR_SDO Max. Delay After SR_SCLK Rising Edge 13 ns
t
DSDODAI1
1, 3
SR_SDO Hold After DAI_P08–01 (SR_SCLK) Rising Edge 3 ns
t
DSDODAI2
1, 3
SR_SDO Max. Delay After DAI_P08–01 (SR_SCLK) Rising Edge 13 ns
t
DSDOSP1
3, 4
SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge –2 ns
t
DSDOSP2
3, 4
SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge 5 ns
t
DSDOPCG1
3, 5, 6
SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge –2 ns
t
DSDOPCG2
3, 5, 6
SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge 5 ns
t
DSDOCLR1
3
SR_CLR to SR_SDO Min. Delay 4 ns
t
DSDOCLR2
3
SR_CLR to SR_SDO Max. Delay 13 ns
t
DLDO1
3
SR_LDO Hold After SR_LAT Rising Edge 3 ns
t
DLDO2
3
SR_LDO Max. Delay After SR_LAT Rising Edge 13 ns
t
DLDODAI1
3
SR_LDO Hold After DAI_P08–01 (SR_LAT) Rising Edge 3 ns
t
DLDODAI2
3
SR_LDO Max. Delay After DAI_P08–01 (SR_LAT) Rising Edge 13 ns
t
DLDOSP1
3,
4
SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge –2 ns
t
DLDOSP2
3, 4
SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge 5 ns
t
DLDOPCG1
3, 5, 6
SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge –2 ns
t
DLDOPCG2
3,
5, 6
SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge 5 ns
t
DLDOCLR1
3
SR_CLR to SR_LDO Min. Delay 4 ns
t
DLDOCLR2
3
SR_CLR to SR_LDO Max. Delay 14 ns
1
Any of the DAI_P08–01 pins can be routed to the shift register clock, latch clock and serial data input via the SRU.
2
Both clocks can be connected to the same clock source. If both clocks are connected to same clock source, then data in the 18-stage shift register is always one cycle ahead of
latch register data.
3
For setup/hold timing requirements of off-chip shift register interfacing devices.
4
SPORTx serial clock out, frame sync out, and serial data outputs are routed to shift register block internally and are also routed onto DAI_P20–01.
5
PCG serial clock output is routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SR_LAT and SDI internally.
6
PCG Serial clock and frame sync outputs are routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SDI internally.