Datasheet

Rev. C | Page 48 of 76 | July 2013
ADSP-21477/ADSP-21478/ADSP-21479
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 40. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the PDAP, see the
PDAP chapter of the ADSP-214xx SHARC Processor Hardware
Reference. Note that the 20 bits of external PDAP data can be
provided through the ADDR23–0 pins or over the DAI pins.
Table 40. Parallel Data Acquisition Port (PDAP)
88-Lead LFCSP Package All Other Packages
Unit
Parameter Min Max Min Max
Timing Requirements
t
SPHOLD
1
PDAP_HOLD Setup Before PDAP_CLK Sample Edge 4 2.5 ns
t
HPHOLD
1
PDAP_HOLD Hold After PDAP_CLK Sample Edge 4 2.5 ns
t
PDSD
1
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 5 3.85 ns
t
PDHD
1
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 4 2.5 ns
t
PDCLKW
Clock Width (t
PCLK
× 4) ÷ 2 – 3 (t
PCLK
× 4) ÷ 2 – 3 ns
t
PDCLK
Clock Period t
PCLK
× 4 t
PCLK
× 4 ns
Switching Characteristics
t
PDHLDD
Delay of PDAP Strobe After Last PDAP_CLK
Capture Edge for a Word
2 × t
PCLK
+ 3 2 × t
PCLK
+ 3 ns
t
PDSTRB
PDAP Strobe Pulse Width 2 × t
PCLK
– 1.5 2 × t
PCLK
– 1.5 ns
1
Source pins of DATA and control are ADDR23–0 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
Figure 27. PDAP Timing
DAI_P20–1
(PDAP_CLK)
SAMPLE EDGE
DAI_P20–1
(PDAP_HOLD)
DAI_P20–1
(PDAP_STROBE)
t
PDSTRB
t
PDHLDD
t
PDHD
t
PDSD
t
SPHOLD
t
HPHOLD
t
PDCLK
t
PDCLKW
DAI_P20–1/
ADDR23–4
(PDAP_DATA)