Datasheet

ADSP-21477/ADSP-21478/ADSP-21479
Rev. C | Page 43 of 76 | July 2013
Figure 22. Serial Ports
DRIVE EDGE SAMPLE EDGE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(FS)
DAI_P20–1
(SCLK)
t
HOFSIR
t
HFSI
t
HDRI
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(FS)
DAI_P20–1
(SCLK)
t
HFSI
t
DDTI
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(FS)
DAI_P20–1
(SCLK)
t
HOFSE
t
HOFSI
t
HDTI
t
HFSE
t
HDTE
t
DDTE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(FS)
DAI_P20–1
(SCLK)
t
HOFSE
t
HFSE
t
HDRE
DATA RECEIVE—EXTERNAL CLOCK
t
SCLKIW
t
DFSIR
t
SFSI
t
SDRI
t
SCLKW
t
DFSE
t
SFSE
t
SDRE
t
DFSE
t
SFSE
t
SFSI
t
DFSI
t
SCLKIW
t
SCLKW