Datasheet

Rev. C | Page 42 of 76 | July 2013
ADSP-21477/ADSP-21478/ADSP-21479
Table 35. Serial Ports—Internal Clock
88-Lead LFCSP Package All Other Packages
Unit
Parameter Min Max Min Max
Timing Requirements
t
SFSI
1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in Either Transmit
or Receive Mode)
13 10.5 ns
t
HFSI
1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in Either Transmit
or Receive Mode)
2.5 2.5 ns
t
SDRI
1
Receive Data Setup Before SCLK 13 10.5 ns
t
HDRI
1
Receive Data Hold After SCLK 2.5 2.5 ns
Switching Characteristics
t
DFSI
2
Frame Sync Delay After SCLK (Internally Generated
Frame Sync in Transmit Mode)
55ns
t
HOFSI
2
Frame Sync Hold After SCLK (Internally Generated
Frame Sync in Transmit Mode)
–1.0 –1.0 ns
t
DFSIR
2
Frame Sync Delay After SCLK (Internally Generated
Frame Sync in Receive Mode)
10.7 10.7 ns
t
HOFSIR
2
Frame Sync Hold After SCLK (Internally Generated
Frame Sync in Receive Mode)
–1.0 –1.0 ns
t
DDTI
2
Transmit Data Delay After SCLK 4 4 ns
t
HDTI
2
Transmit Data Hold After SCLK –1.0 –1.0 ns
t
SCKLIW
Transmit or Receive SCLK Width 2 × t
PCLK
– 1.5 2 × t
PCLK
+ 1.5 2 × t
PCLK
– 1.5 2 × t
PCLK
+ 1.5 ns
1
Referenced to the sample edge.
2
Referenced to drive edge.