Datasheet

ADSP-21477/ADSP-21478/ADSP-21479
Rev. C | Page 41 of 76 | July 2013
Serial Ports
In slave transmitter mode and master receiver mode, the maxi-
mum serial port frequency is f
PCLK
/8. In master transmitter
mode and slave receiver mode, the maximum serial port clock
frequency is f
PCLK
/4.
To determine whether communication is possible between two
devices at clock speed, n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, Data Channel A, Data Channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 34. Serial Ports—External Clock
88-Lead LFCSP Package All Other Packages
Unit
Parameter Min Max Min Max
Timing Requirements
t
SFSE
1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in Either Transmit or
Receive Mode)
42.5ns
t
HFSE
1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in Either Transmit or
Receive Mode)
42.5ns
t
SDRE
1
Receive Data Setup Before Receive SCLK 4 2.5 ns
t
HDRE
1
Receive Data Hold After SCLK 4 2.5 ns
t
SCLKW
SCLK Width (t
PCLK
× 4) ÷ 2 – 1.5 (t
PCLK
× 4) ÷ 2 – 1.5 ns
t
SCLK
SCLK Period t
PCLK
× 4 t
PCLK
× 4 ns
Switching Characteristics
t
DFSE
2
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in Either Transmit or
Receive Mode)
15 15 ns
t
HOFSE
2
Frame Sync Hold After SCLK
(Internally Generated Frame Sync in Either Transmit or
Receive Mode)
22ns
t
DDTE
2
Transmit Data Delay After Transmit SCLK 15 15 ns
t
HDTE
2
Transmit Data Hold After Transmit SCLK 2 2 ns
1
Referenced to sample edge.
2
Referenced to drive edge.