Datasheet

ADSP-21477/ADSP-21478/ADSP-21479
Rev. C | Page 39 of 76 | July 2013
AMI Write
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD
,
AMI_WR
, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 33. AMI Write
Parameter Min Max Unit
Timing Requirements
t
DAAK
AMI_ACK Delay from Address Selects
1, 2
t
SDCLK
– 10.1 + W ns
t
DSAK
AMI_ACK Delay from AMI_WR Low
1, 3
W – 7.1 ns
Switching Characteristics
t
DAWH
Address Selects to AMI_WR Deasserted
2
t
SDCLK
–4.4 + W ns
t
DAWL
Address Selects to AMI_WR Low
2
t
SDCLK
– 4.5 ns
t
WW
AMI_WR Pulse Width W – 1.3 ns
t
DDWH
Data Setup Before AMI_WR High t
SDCLK
– 4.3 + W ns
t
DWHA
Address Hold After AMI_WR Deasserted H ns
t
DWHD
Data Hold After AMI_WR Deasserted H ns
t
DATRWH
Data Disable After AMI_WR Deasserted
4
t
SDCLK
– 1.37 + H t
SDCLK
+ 6.75+ H ns
t
WWR
AMI_WR High to AMI_WR Low
5
t
SDCLK
– 1.5+ H ns
t
DDWR
Data Disable Before AMI_RD Low 2 × t
SDCLK
– 7.1 ns
t
WDE
AMI_WR Low to Data Enabled t
SDCLK
– 4.5 ns
W = (number of wait states specified in AMICTLx register) × t
SDCLK
H = (number of hold cycles specified in AMICTLx register) × t
SDCLK
1
AMI_ACK delay/setup: System must meet t
DAAK
, or t
DSAK
, for deassertion of AMI_ACK (low).
2
The falling edge of AMI_MSx is referenced.
3
Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.
4
See Test Conditions on Page 65 for calculation of hold times given capacitive and dc loads.
5
For Write to Write: t
SDCLK
+ H, for both same bank and different bank. For Write to Read: 3 × t
SDCLK
+ H, for the same bank and different banks.