Datasheet

Rev. C | Page 36 of 76 | July 2013
ADSP-21477/ADSP-21478/ADSP-21479
SDRAM Interface Timing
Table 31. SDRAM Interface Timing
133 MHz 150 MHz
UnitParameter Min Max Min Max
Timing Requirements
t
SSDAT
DATA Setup Before SDCLK 0.7 0.7 ns
t
HSDAT
DATA Hold After SDCLK 1.66 1.5 ns
Switching Characteristics
t
SDCLK
1
1
Systems should use the SDRAM model with a speed grade higher than the desired SDRAM controller speed. For example, to run the SDRAM controller at 133 MHz the
SDRAM model with a speed grade of 143 MHz or above should be used. See Engineer-to-Engineer Note “Interfacing SDRAM memory to SHARC processors (EE-286)” for
more information on hardware design guidelines for the SDRAM interface.
SDCLK Period 7.5 6.66 ns
t
SDCLKH
SDCLK Width High 2.5 2.2 ns
t
SDCLKL
SDCLK Width Low 2.5 2.2 ns
t
DCAD
2
2
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDQM, SDCKE.
Command, ADDR, Data Delay After SDCLK 5 4.75 ns
t
HCAD
2
Command, ADDR, Data Hold After SDCLK 1 1 ns
t
DSDAT
Data Disable After SDCLK 6.2 5.3 ns
t
ENSDAT
Data Enable After SDCLK 0.3 0.3 ns
Figure 19. SDRAM Interface Timing
SDCLK
DATA (IN)
DATA (OUT)
COMMAND/ADDR
(OUT)
t
SDCLKH
t
SDCLKL
t
HSDAT
t
SSDAT
t
HCAD
t
DCAD
t
ENSDAT
t
DCAD
t
DSDAT
t
HCAD
t
SDCLK