Datasheet

Rev. C | Page 32 of 76 | July 2013
ADSP-21477/ADSP-21478/ADSP-21479
Timer WDTH_CAP Timing
The following timing specification applies to timer0 and timer1,
and in WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DPI_P14–1 pins through the
SRU. Therefore, the timing specification provided below is valid
at the DPI_P14–1 pins.
Watchdog Timer Timing
Table 26. Timer Width Capture Timing
Parameter Min Max Unit
Timing Requirement
t
PWI
Timer Pulse Width 2 × t
PCLK
2 × (2
31
– 1) × t
PCLK
ns
Figure 14. Timer Width Capture Timing
TIMER
CAPTURE
INPUTS
t
PWI
Table 27. Watchdog Timer Timing
Parameter Min Max Unit
Timing Requirement
t
WDTCLKPER
100 1000 ns
Switching Characteristics
t
RST
WDT Clock Rising Edge to Watchdog Timer
RESET Falling Edge
37.6 ns
t
RSTPW
Reset Pulse Width 64 × t
WDTCLKPER
1
ns
1
When the internal oscillator is used, the 1/t
WDTCLKPER
varies from 1.5 MHz to 2.5 MHz and the WDT_CLKIN pin should be pulled low.
Figure 15. Watchdog Timer Timing
WDT_CLKIN
WDTRSTO
t
WDTCLKPER
t
RST
t
RSTPW