Datasheet

Rev. C | Page 28 of 76 | July 2013
ADSP-21477/ADSP-21478/ADSP-21479
Clock Input
Table 20. Clock Input
Parameter
200 MHz 266 MHz 300 MHz
Unit
Min Max Min Max Min Max
Timing Requirements
t
CK
CLKIN Period 40 100 30
1
1
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
100 26.66
1
100 ns
t
CKL
CLKIN Width Low 20 45 15 45 13.33 45 ns
t
CKH
CLKIN Width High 20 45 15 45 13.33 45 ns
t
CKRF
CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 ns
t
CCLK
2
2
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
cclk
.
CCLK Period 5 10 3.75 10 3.33 10 ns
f
VCO
3
3
See Figure 5 on Page 26 for VCO diagram.
VCO Frequency 200 600 200 600 200 600 MHz
t
CKJ
4, 5
4
Actual input jitter should be combined with ac specifications for accurate timing analysis.
5
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
CLKIN Jitter Tolerance –250 +250 –250 +250 –250 +250 ps
Figure 7. Clock Input
CLKIN
t
CK
t
CKL
t
CKH
t
CKJ