Datasheet

ManualsBrandsANALOG DEVICES ManualsMicrocontrollers, Microprocessors & QuartzesDigital signal processor (DSP) LQFP 100 EP (14x14) 1.2 V 200 MHz

ADSP-21477/ADSP-21478/ADSP-21479

Rev. C | Page 63 of 76 | July 2013

Figure 44. SR_SCLK to SR_LAT Setup, Clocks Pulse Width and Maximum Frequency

Figure 45. Shift Register Reset Timing

SR_SCLK

OR

DAI_P08

-

01

SR_SDI

OR

DAI_P08

-

01

SR_LDO

SR_LAT

OR

DAI_P08

-

01

t

SSCK2LCKDAI

t

SSCK2LCK

SR_SDCLK

OR

DAI_P08

-

01

SR_LDO

SR_LAT

OR

DAI_P08

-

01

t

DSDOCLR2

t

DSDOCLR1

t

DLDOCLR2

t

DLDOCLR1

t

CLRW

t

CLRREM2SCK

t

CLRREM2LCK

SR_CLR

SR_SDO