Datasheet

ADSP-21477/ADSP-21478/ADSP-21479
Rev. C | Page 57 of 76 | July 2013
SPI Interface—Slave
Table 51. SPI Interface Protocol—Slave Switching and Timing Specifications
88-Lead LFCSP Package All Other Packages
Unit
Parameter Min Max Min Max
Timing Requirements
t
SPICLKS
Serial Clock Cycle 4 × t
PCLK
– 2 4 × t
PCLK
– 2 ns
t
SPICHS
Serial Clock High Period 2 × t
PCLK
– 2 2 × t
PCLK
– 2 ns
t
SPICLS
Serial Clock Low Period 2 × t
PCLK
– 2 2 × t
PCLK
– 2 ns
t
SDSCO
SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1 2 × t
PCLK
2 × t
PCLK
ns
t
HDS
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × t
PCLK
2 × t
PCLK
ns
t
SSPIDS
Data Input Valid to SPICLK Edge (Data Input Setup Time) 2 2 ns
t
HSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid 2 2 ns
t
SDPPW
SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × t
PCLK
2 × t
PCLK
ns
Switching Characteristics
t
DSOE
SPIDS Assertion to Data Out Active 0 13 0 10.25 ns
t
DSOE
1
SPIDS Assertion to Data Out Active (SPI2) 0 13 0 10.25 ns
t
DSDHI
SPIDS Deassertion to Data High Impedance 0 2 × t
PCLK
013.25 ns
t
DSDHI
1
SPIDS Deassertion to Data High Impedance (SPI2) 0 2 × t
PCLK
013.25 ns
t
DDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time) 13 11.5 ns
t
HDSPIDS
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t
PCLK
2 × t
PCLK
ns
t
DSOV
SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t
PCLK
5 × t
PCLK
ns
1
The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral
Interface Port (SPI)” chapter.
Figure 37. SPI Slave Timing
t
SPICHS
t
SPICLS
t
SPICLKS
t
HDS
t
SDPPW
t
SDSCO
t
DSOE
t
DDSPIDS
t
DDSPIDS
t
DSDHI
t
HDSPIDS
t
HSPIDS
t
SSPIDS
t
DSDHI
t
DSOV
t
HSPIDS
t
HDSPIDS
SPIDS
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
CPHASE = 1
CPHASE = 0
SPICLK
(CP = 0,
CP = 1)
(INPUT)
t
SSPIDS