Datasheet

Rev. C | Page 56 of 76 | July 2013
ADSP-21477/ADSP-21478/ADSP-21479
SPI Interface—Master
Both the primary and secondary SPIs are available through DPI
only. The timing provided in Table 50 and Table 51 applies
to both.
Table 50. SPI Interface Protocol—Master Switching and Timing Specifications
88-Lead LFCSP Package All Other Packages
Unit
Parameter Min Max Min Max
Timing Requirements
t
SSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time) 10 8.6 ns
t
HSPIDM
SPICLK Last Sampling Edge to Data Input Not Valid 2 2 ns
Switching Characteristics
t
SPICLKM
Serial Clock Cycle 8 × t
PCLK
– 2 8 × t
PCLK
– 2 ns
t
SPICHM
Serial Clock High Period 4 × t
PCLK
– 2 4 × t
PCLK
– 2 ns
t
SPICLM
Serial Clock Low Period 4 × t
PCLK
– 2 4 × t
PCLK
– 2 ns
t
DDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay time) 2.5 2.5
t
HDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold time) 4 × t
PCLK
– 2 4 × t
PCLK
– 2 ns
t
SDSCIM
DPI Pin (SPI Device Select) Low to First SPICLK Edge 4 × t
PCLK
– 2 4 × t
PCLK
– 2 ns
t
HDSM
Last SPICLK Edge to DPI Pin (SPI Device Select) High 4 × t
PCLK
– 2 4 × t
PCLK
– 2 ns
t
SPITDM
Sequential Transfer Delay 4 × t
PCLK
– 2 4 × t
PCLK
– 1.4 ns
Figure 36. SPI Master Timing
t
SPICHM
t
SDSCIM
t
SPICLM
t
SPICLKM
t
HDSM
t
SPITDM
t
DDSPIDM
t
HSPIDM
t
SSPIDM
DPI
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
CPHASE = 1
CPHASE = 0
t
HDSPIDM
t
HSPIDM
t
HSPIDM
t
SSPIDM
t
SSPIDM
t
DDSPIDM
t
HDSPIDM
SPICLK
(CP = 0,
CP = 1)
(OUTPUT)