Datasheet

ADSP-21477/ADSP-21478/ADSP-21479
Rev. C | Page 55 of 76 | July 2013
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 49. S/PDIF Receiver Internal Digital PLL Mode Timing
Parameter Min Max Unit
Switching Characteristics
t
DFSI
FS Delay After Serial Clock 5 ns
t
HOFSI
FS Hold After Serial Clock –2 ns
t
DDTI
Transmit Data Delay After Serial Clock 5 ns
t
HDTI
Transmit Data Hold After Serial Clock –2 ns
t
SCLKIW
1
Transmit Serial Clock Width 38.5 ns
1
The serial clock frequency is 64 × frame sync (FS) where FS = the frequency of LRCLK.
Figure 35. S/PDIF Receiver Internal Digital PLL Mode Timing
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
DRIVE EDGE
t
SCLKIW
t
DFSI
t
HOFSI
t
DDTI
t
HDTI