Datasheet

Rev. C | Page 54 of 76 | July 2013
ADSP-21477/ADSP-21478/ADSP-21479
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in Table 47. Input signals are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter requires an oversampling clock input.
This high frequency clock (TxCLK) input is divided down to
generate the internal biphase clock.
Table 47. S/PDIF Transmitter Input Data Timing
88-Lead LFCSP Package All Other Packages
Unit
Parameter Min Max Min Max
Timing Requirements
t
SISFS
1
Frame Sync Setup Before Serial Clock Rising Edge 4.5 3 ns
t
SIHFS
1
Frame Sync Hold After Serial Clock Rising Edge 3 3 ns
t
SISD
1
Data Setup Before Serial Clock Rising Edge 4.5 3 ns
t
SIHD
1
Data Hold After Serial Clock Rising Edge 3 3 ns
t
SITXCLKW
Transmit Clock Width 9 9 ns
t
SITXCLK
Transmit Clock Period 20 20 ns
t
SISCLKW
Clock Width 36 36 ns
t
SISCLK
Clock Period 80 80 ns
1
The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input
can be either CLKIN or any of the DAI pins.
Figure 34. S/PDIF Transmitter Input Timing
SAMPLE EDGE
DAI_P20–1
(TxCLK)
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
t
SITXCLKW
t
SITXCLK
t
SISCLKW
t
SISCLK
t
SISFS
t
SIHFS
t
SISD
t
SIHD
Table 48. Oversampling Clock (TxCLK) Switching Characteristics
Parameter Max Unit
Frequency for TxCLK = 384 × Frame Sync Oversampling Ratio × Frame Sync ≤ 1/t
SITXCLK
MHz
Frequency for TxCLK = 256 × Frame Sync 49.2 MHz
Frame Rate (FS) 192.0 kHz