Datasheet

ADSP-21477/ADSP-21478/ADSP-21479
Rev. C | Page 47 of 76 | July 2013
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 39. IDP
signals are routed to the DAI_P20–1 pins using the SRU. There-
fore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 39. Input Data Port (IDP)
88-Lead LFCSP Package All Other Packages
Unit
Parameter Min Max Min Max
Timing Requirements
t
SISFS
1
Frame Sync Setup Before Serial Clock Rising Edge 4.5 3.8 ns
t
SIHFS
1
Frame Sync Hold After Serial Clock Rising Edge 3 2.5 ns
t
SISD
1
Data Setup Before Serial Clock Rising Edge 4 2.5 ns
t
SIHD
1
Data Hold After Serial Clock Rising Edge 3 2.5 ns
t
IDPCLKW
Clock Width (t
PCLK
× 4) ÷ 2 – 1 (t
PCLK
× 4) ÷ 2 – 1 ns
t
IDPCLK
Clock Period t
PCLK
× 4 t
PCLK
× 4 ns
1
The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The PCG’s input
can be either CLKIN or any of the DAI pins.
Figure 26. IDP Master Timing
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
t
IPDCLK
t
IPDCLKW
t
SISFS
t
SIHFS
t
SIHD
t
SISD