Datasheet

Rev. C | Page 44 of 76 | July 2013
ADSP-21477/ADSP-21478/ADSP-21479
Table 36. Serial Ports—External Late Frame Sync
88-Lead LFCSP Package All Other Packages
Unit
Parameter Min Max Min Max
Switching Characteristics
t
DDTLFSE
1
Data Delay from Late External Transmit Frame Sync or
External Receive Frame Sync with MCE = 1, MFD = 0
2 × t
PCLK
13.5
ns
t
DDTENFS
1
Data Enable for MCE = 1, MFD = 0 0.5 0.5 ns
1
The t
DDTLFSE
and t
DDTENFS
parameters apply to left-justified as well as DSP serial mode, and MCE = 1, MFD = 0.
Figure 23. External Late Frame Sync
1
1
This figure reflects changes made to support left-justified mode.
DRIVE SAMPLE
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
2ND BIT
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
1ST BIT
DRIVE
t
DDTE/I
t
HDTE/I
t
DDTLFSE
t
DDTENFS
t
SFSE/I
DRIVE SAMPLE
LATE EXTERNAL TRANSMIT FS
2ND BIT
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
1ST BIT
DRIVE
t
DDTE/I
t
HDTE/I
t
DDTLFSE
t
DDTENFS
t
SFSE/I
t
HFSE/I
t
HFSE/I