Datasheet

ADSP-21477/ADSP-21478/ADSP-21479
Rev. C | Page 31 of 76 | July 2013
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (TMREXP).
Timer PWM_OUT Cycle Timing
The following timing specification applies to timer0 and timer1
in PWM_OUT (pulse-width modulation) mode. Timer signals
are routed to the DPI_P14–1 pins through the DPI SRU. There-
fore, the timing specifications provided below are valid at the
DPI_P14–1 pins.
Table 24. Core Timer
88-Lead LFCSP Package All Other Packages
Unit
Parameter Min Max Min Max
Switching Characteristic
t
WCTIM
TMREXP Pulse Width 4 × t
PCLK
– 1.55 4 × t
PCLK
– 1.2 ns
Figure 12. Core Timer
FLAG3
(TMREXP)
t
WCTIM
Table 25. Timer PWM_OUT Timing
88-Lead LFCSP Package All Other Packages
Unit
Parameter Min Max Min Max
Switching Characteristic
t
PWMO
Timer Pulse Width Output 2 × t
PCLK
– 1.65 2 × (2
31
– 1) × t
PCLK
2 × t
PCLK
– 1.2 2 × (2
31
– 1) × t
PCLK
ns
Figure 13. Timer PWM_OUT Timing
PWM
OUTPUTS
t
PWMO