Datasheet

ADSP-21477/ADSP-21478/ADSP-21479
Rev. C | Page 29 of 76 | July 2013
Clock Signals
The processors can use an external clock or a crystal. See the
CLKIN pin description in Table 11. Programs can configure the
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL. Figure 8 shows the
component connections used for a crystal operating in funda-
mental mode. Note that the clock rate is achieved using a
16.67 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve
the full core clock rate, programs need to configure the multi-
plier bits in the PMCTL register.
Reset
Figure 8. 266 MHz Operation (Fundamental Mode Crystal)
C
1
2
2pF
Y1
R1
1MΩ *
XTAL
CLKIN
C2
22pF
16.67
R2
47Ω *
ADSP-2147x
CHOOSE C1 AND C2 BASED ON THE CRYSTAL Y1.
CHOOSE R2 TO LIMIT CRYSTAL DRIVE POWER.
REFER TO CRYSTAL MANUFACTURER'S SPECIFICATIONS
*TYPICAL VALUES
Table 21. Reset
Parameter Min Max Unit
Timing Requirements
t
WRST
1
RESET Pulse Width Low 4 × t
CK
ns
t
SRST
RESET Setup Before CLKIN Low 8 ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable
V
DD
and CLKIN (not including start-up time of external clock oscillator).
Figure 9. Reset
CLKIN
RESET
t
SRST
t
WRST