Datasheet

ADSP-21469
Rev. 0 | Page 59 of 72 | June 2010
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Table 55). Figure 52 through Figure 57
show graphically how output delays and holds vary with load
capacitance. The graphs of Figure 48 through Figure 57 may not
be linear outside the ranges shown for Typical Output Delay vs.
Load Capacitance and Typical Output Rise Time (20% to 80%,
V = Min) vs. Load Capacitance.
Figure 47. Output Buffer Characteristics (Worst-Case DDR2)
Figure 48. Typical Output Rise/Fall Time Non-DDR2
(20% to 80%, V
DD_EXT
= Max)
SWEEP (V
DDEXT
) VOLTAGE (V)
0
0
30
50
SOURCE (V
DDEXT
) CURRENT (mA)
40
20
- 50
V
OH
3.13 V, 125 °C
V
OL
3.13 V, 125 °C
10
- 30
- 40
- 20
- 10
1.5
0.5 1.0
TYPE C & D, HALF DRIVE
TYPE C & D, FULL DRIVE
TYPE C & D, HALF DRIVE
TYPE C & D, FULL DRIVE
LOAD CAPACITANCE (pF)
6
0
0
7
4
2
1
3
RISE AND FALL TIMES (ns)
125 20010025 17550 75 150
5
y = 0.0342x + 0.309
y = 0.0153x + 0.2131
y = 0.0413x + 0.2651
y = 0.0152x + 0.1882
TYPE A DRIVE FALL
TYPE A DRIVE RISE
TYPE B DRIVE FALL
TYPE B DRIVE RISE
Figure 49. Typical Output Rise/Fall Time Non-DDR2
(20% to 80%, V
DD_EXT
= Min)
Figure 50. Typical Output Rise/Fall Time DDR2
(20% to 80%, V
DD_EXT
= Max)
LOAD CAPACITANCE (pF)
6
0
0
10
4
2
RISE AND FALL TIMES (ns)
25 20015050 75 100 125 175
y = 0.0746x + 0.5146
y = 0.0572x + 0.5571
y = 0.0278x + 0.3138
y = 0.0258x + 0.3684
TYPE A FALL
TYPE A RISE
TYPE B RISE
TYPE B FALL
8
12
14
LOAD CAPACITANCE (pF)
0.6
0
0.7
0.4
0.2
0.1
0.3
RISE AND FALL TIMES (ns)
0.5
y = 0.0058x + 0.2113
y = 0.0217x + 0.26
y = 0.0198x + 0.2304
y = 0.0061x + 0.207
05 403010 15 20 25 35
TYPE C & D HALF DRIVE FALL
0.8
0.9
1.0
TYPE C & D HALF DRIVE RISE
TYPE C & D FULL DRIVE RISE
TYPE C & D FULL DRIVE FALL