Datasheet

Rev. 0 | Page 48 of 72 | June 2010
ADSP-21469
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left-justified, I
2
S, or right-justified with word widths of 16, 18,
20, or 24 bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 33 shows the right-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is delayed minimum in
24-bit output mode or maximum in 16-bit output mode from
an LRCLK transition, so that when there are 64 serial clock peri-
ods per LRCLK period, the LSB of the data will be right-justified
to the next LRCLK transition.
Figure 34 shows the default I
2
S-justified mode. LRCLK is low
for the left channel and HI for the right channel. Data is valid on
the rising edge of serial clock. The MSB is left-justified to an
LRCLK transition but with a delay.
Figure 35 shows the left-justified mode. LRCLK is high for the
left channel and LO for the right channel. Data is valid on the
rising edge of serial clock. The MSB is left-justified to an LRCLK
transition with no delay.
Table 44. S/PDIF Transmitter Right-Justified Mode
Parameter Nominal Unit
Timing Requirement
t
RJD
LRCLK to MSB Delay in Right-Justified Mode
16-Bit Word Mode
18-Bit Word Mode
20-Bit Word Mode
24-Bit Word Mode
16
14
12
8
SCLK
SCLK
SCLK
SCLK
Figure 33. Right-Justified Mode
Table 45. S/PDIF Transmitter I
2
S Mode
Parameter Nominal Unit
Timing Requirement
t
I 2 SD
LRCLK to MSB Delay in I
2
S Mode 1 SCLK
Figure 34. I
2
S-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSB LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
LRCLK
DAI_P20–1
SCLK
DAI_P20–1
SDATA
t
RJD
MSB
LEFT/RIGHT CHANNEL
LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
LRCLK
DAI_P20–1
SCLK
DAI_P20–1
SDATA
t
I2SD