Datasheet

Rev. 0 | Page 46 of 72 | June 2010
ADSP-21469
Sample Rate Converter—Serial Output Port
For the serial output port, the frame sync is an input and it
should meet setup and hold times with regard to the serial clock
on the output port. The serial data output has a hold time and
delay specification with regard to serial clock. Note that the
serial clock rising edge is the sampling edge, and the falling edge
is the drive edge.
Table 42. ASRC, Serial Output Port
Parameter Min Max Unit
Timing Requirements
t
SRCSFS
1
Frame Sync Setup Before Serial Clock Rising Edge 4 ns
t
SRCHFS
1
Frame Sync Hold After Serial Clock Rising Edge 5.5 ns
t
SRCCLKW
Clock Width (t
PCLK
× 4) ÷ 2 – 1 ns
t
SRCCLK
Clock Period t
PCLK
× 4 ns
Switching Characteristics
t
SRCTDD
1
Transmit Data Delay After Serial Clock Falling Edge 9.9 ns
t
SRCTDH
1
Transmit Data Hold After Serial Clock Falling Edge 1 ns
1
The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input
can be either CLKIN or any of the DAI pins.
Figure 31. ASRC Serial Output Port Timing
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
t
SRCCLK
t
SRCCLKW
t
SRCSFS
t
SRCHFS
t
SRCTDD
t
SRCTDH