Datasheet

Rev. 0 | Page 44 of 72 | June 2010
ADSP-21469
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 40. PDAP is the parallel mode operation of channel 0 of
the IDP. For details on the operation of the PDAP, see the
PDAP chapter of the ADSP-214xx SHARC Processor Hardware
Reference. Note that the 20 bits of external PDAP data can be
provided through the AMI_ADDR23–4 pins or over the DAI
pins.
Table 40. Parallel Data Acquisition Port (PDAP)
Parameter Min Max Unit
Timing Requirements
t
SPHOLD
1
PDAP_HOLD Setup Before PDAP_CLK Sample Edge 2.5 ns
t
HPHOLD
1
PDAP_HOLD Hold After PDAP_CLK Sample Edge 2.5 ns
t
PDSD
1
PDAP_DAT Setup Before Serial Clock PDAP_CLK Sample Edge 3.85 ns
t
PDHD
1
PDAP_DAT Hold After Serial Clock PDAP_CLK Sample Edge 2.5 ns
t
PDCLKW
Clock Width (t
PCLK
× 4) ÷ 2 – 3 ns
t
PDCLK
Clock Period t
PCLK
× 4 ns
Switching Characteristics
t
PDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t
PCLK
+ 3 ns
t
PDSTRB
PDAP Strobe Pulse Width 2 × t
PCLK
– 1 ns
1
Data source pins are AMI_ADDR23–4 or DAI pins. Source pins for serial clock and frame sync are 1) AMI_ADDR3–2 pins, 2) DAI pins.
Figure 29. PDAP Timing
DAI_P20–1
(PDAP_CLK)
SAMPLE EDGE
DAI_P20–1
(PDAP_HOLD)
DAI_P20–1
(PDAP_STROBE)
t
PDSTRB
t
PDHLDD
t
PDHD
t
PDSD
t
SPHOLD
t
HPHOLD
t
PDCLK
t
PDCLKW
DAI_P20–1/
ADDR23–4
(PDAP_DATA)