Datasheet

ADSP-21469
Rev. 0 | Page 35 of 72 | June 2010
AMI Write
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD
,
AMI_WR
, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 31. Memory Write
Parameter Min Max Unit
Timing Requirements
t
DAAK
AMI_ACK Delay from Address, Selects
1, 2
t
DDR 2_ CLK
– 9.7 + W ns
t
DSAK
AMI_ACK Delay from AMI_WR Low
1, 3
W – 6 ns
Switching Characteristics
t
DAWH
Address, Selects to AMI_WR Deasserted
2
t
DDR 2_ CLK
–3.1+ W ns
t
DAWL
Address, Selects to AMI_WR Low
2
t
DDR 2_ CLK
–3 ns
t
WW
AMI_WR Pulse Width W – 1.3 ns
t
DDWH
Data Setup Before AMI_WR High t
DDR 2_ CLK
–3.0+ W ns
t
DWHA
Address Hold After AMI_WR Deasserted H + 0.15 ns
t
DWHD
Data Hold After AMI_WR Deasserted H ns
t
DATRWH
Data Disable After AMI_WR Deasserted
4
t
DDR 2_ CLK
– 1.37 + H t
DDR 2_ CLK
+ 4.9 + H ns
t
WWR
AMI_WR High to AMI_WR Low
5
t
DDR 2_ CLK
–1.5+ H ns
t
DDWR
Data Disable Before AMI_RD Low 2t
DDR 2_ CLK
– 6 ns
t
WDE
AMI_WR Low to Data Enabled t
DDR 2_ CLK
– 3.5 ns
W = (number of wait states specified in AMICTLx register) × t
SDDR 2_ CLK
H = (number of hold cycles specified in AMICTLx register) × t
DDR 2_ CLK
1
AMI_ACK delay/setup: System must meet t
DAAK
, or t
DSAK
, for deassertion of AMI_ACK (low).
2
The falling edge of AMI_MSx is referenced.
3
Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.
4
See Test Conditions on Page 58 for calculation of hold times given capacitive and dc loads.
5
For Write to Write: t
DDR2_CLK
+ H, for both same bank and different bank. For Write to Read: (3 × t
DDR2_CLK
) + H, for the same bank and different banks.
Figure 21. AMI Write
AMI_ACK
AMI_DATA
t
DAWH
t
DWHA
t
WWR
t
DATRWH
t
DWHD
t
WW
t
DDWR
t
DDWH
t
DAWL
t
WDE
t
DSAK
t
DAAK
AMI_RD
AMI_WR
AMI_ADDR
AMI_MSx