Datasheet

Rev. 0 | Page 32 of 72 | June 2010
ADSP-21469
DDR2 SDRAM Write Cycle Timing
Table 29. DDR2 SDRAM Write Cycle Timing, V
DD-DDR2
Nominal 1.8 V
200 MHz
1
1
In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed (see Engineer-to-Engineer Note No: EE-349).
225 MHz
1
Parameter Min Max Min Max Unit
Switching Characteristics
t
CK
Clock Cycle Time 4.8 4.22 ns
t
CH
Minimum Clock Pulse Width 2.35 2.75 2.05 2.45 ns
t
CL
Maximum Clock Pulse Width 2.35 2.75 2.05 2.45 ns
t
DQSS
2
2
Write command to first DQS delay = WL × t
CK
+ t
DQSS
.
DQS Latching Rising Transitions to Associated Clock
Edges
–0.4 0.4 –0.45 0.45 ns
t
DS
Last Data Valid to DQS Delay 0.6 0.5 ns
t
DH
DQS to First Data Invalid Delay 0.65 0.55 ns
t
DSS
DQS Falling Edge to Clock Setup Time 1.95 1.65 ns
t
DSH
DQS Falling Edge Hold Time From CK 2.05 1.8 ns
t
DQSH
DQS Input HIGH Pulse Width 2.05 1.65 ns
t
DQSL
DQS Input LOW Pulse Width 2.0 1.65 ns
t
WPRE
Write Preamble 0.8 0.8 t
CK
t
WPST
Write Postamble 0.5 0.5 t
CK
t
AS
Control/address Maximum Delay From DDCK Rise 1.85 1.65 ns
t
AH
Control/Address Minimum Delay From DDCK Rise 1.0 0.9 ns
Figure 19. DDR2 SDRAM Controller Output AC Timing
t
DS
t
DH
t
DQSS
t
DSH
t
DSS
t
WPRE
t
DQSL
t
DQSH
t
WPST
DDR2_ADDR
DDR2_CTL
t
AS
t
AH
DDR2_DATA/DM
DDR2_CLKx
DDR2_CLKx
DDR2_DQSn
DDR2_DQSn
t
CK
t
CH
t
CL