Datasheet

ADSP-21469
Rev. 0 | Page 31 of 72 | June 2010
DDR2 SDRAM Read Cycle Timing
Table 28. DDR2 SDRAM Read Cycle Timing, V
DD-DDR2
Nominal 1.8 V
200 MHz
1
1
In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed (see Engineer-to-Engineer Note EE-349).
225 MHz
1
Parameter Min Max Min Max Unit
Timing Requirements
t
AC
DQ Output Access Time From CK/CK –1.0 0.7 –1.0 0.7 ns
t
DQSCK
DQS Output Access Time From CK/CK –1.0 0.7 –1.0 0.7 ns
t
DQSQ
DQS-DQ Skew for DQS and Associated DQ Signals 0.450 0.450 ns
t
QH
DQ, DQS Output Hold Time From DQS 1.9 1.71 ns
t
RPRE
Read Preamble 0.6 0.6 t
CK
t
RPST
Read Postamble 0.25 0.25 t
CK
Switching Characteristics
t
CK
Clock Cycle Time 4.8 4.22 ns
t
CH
Minimum Clock Pulse Width 2.35 2.75 2.05 2.45 ns
t
CL
Maximum Clock Pulse Width 2.35 2.75 2.05 2.45 ns
t
AS
Address Setup Time 1.85 1.65 ns
t
AH
Address Hold Time 1.0 0.9 ns
Figure 18. DDR2 SDRAM Controller Input AC Timing
DDR2_CLKx
DDR2_DQSn
t
AC
t
RPRE
t
DQSQ
t
DQSQ
t
QH
t
RPST
DDR2_DATA
DDR2_CLKx
DDR2_DQSn
t
DQSCK
t
CK
t
CH
t
CL
t
AS
t
AH
DDR2_ADDR
DDR2_CTL
t
QH