Datasheet

Rev. 0 | Page 24 of 72 | June 2010
ADSP-21469
Clock Input
Clock Signals
The ADSP-21469 can use an external clock or a crystal. See the
CLKIN pin description in Table 9. Programs can configure the
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL. Figure 8 shows the
component connections used for a crystal operating in funda-
mental mode. Note that the clock rate is achieved using a
25 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN
achieves a clock speed of 400 MHz).
To achieve the full core clock rate, programs need to configure
the multiplier bits in the PMCTL register.
Table 18. Clock Input
Parameter
400 MHz
1
1
Applies to all 400 MHz models. See Ordering Guide on Page 70.
450 MHz
2
2
Applies to all 450 MHz models. See Ordering Guide on Page 70.
UnitMin Max Min Max
Timing Requirements
t
CK
CLKIN Period 15
3
3
Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
100 13.26 100 ns
t
CKL
CLKIN Width Low 7.5 45 6.63 45 ns
t
CKH
CLKIN Width High 7.5 45 6.63 45 ns
t
CKRF
CLKIN Rise/Fall (0.4 V to 2.0 V) 3
4
4
Guaranteed by simulation but not tested on silicon.
3
4
ns
t
CCLK
5
5
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK
.
CCLK Period 2.5 10 2.22 10 ns
f
VCO
6
6
See Figure 5 on Page 22 for VCO diagram.
VCO Frequency 200 900 200 900 MHz
t
CKJ
7, 8
7
Actual input jitter should be combined with ac specifications for accurate timing analysis.
8
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
CLKIN Jitter Tolerance –250 +250 –250 +250 ps
Figure 7. Clock Input
CLKIN
t
CK
t
CKL
t
CKH
t
CKJ
Figure 8. Recommended Circuit for
Fundamental Mode Crystal Operation
C1
22pF
Y1
R1
1M: *
XTAL
CLKIN
C2
22pF
25.000 MHz
R2
47: *
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
ADSP-2146x