Datasheet

ADSP-21469
Rev. 0 | Page 23 of 72 | June 2010
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 17. While no specific power-up sequencing is required
between V
DD _ EXT
, V
DD _ DDR 2
, and V
DD _ INT
, there are some consider-
ations that the system designs should take into account.
• No power supply should be powered up for an extended
period of time (> 200 ms) before another supply starts to
ramp up.
•If V
DD _ INT
power supply comes up after V
DD _ EXT
, any pin,
such as RESETOUT
and RESET, may actually drive
momentarily until the V
DD _ INT
rail has powered up. Systems
sharing these signals on the board must determine if there
are any issues that need to be addressed based on this
behavior.
Note that during power-up, when the V
DD _ INT
power supply
comes up after V
DD _ EXT
, a leakage current of the order of three-
state leakage current pull-up, pull-down may be observed on
any pin, even if that pin is an input only (for example the RESET
pin) until the V
DD _ INT
rail has powered up.
Table 17. Power Up Sequencing Timing Requirements (Processor Startup)
Parameter Min Max Unit
Timing Requirements
t
RSTVDD
RESET Low Before V
DD _ INT
or V
DD _ EXT
or V
DD _ DDR 2
On 0 ms
t
IVDD - EVDD
V
DD _ INT
On Before V
DD _ EXT
–200 +200 ms
t
EVDD _ DDR 2 VDD
V
DD _ EXT
On Before V
DD _ DDR 2
–200 +200 ms
t
CLKVDD
1
CLKIN Valid After V
DD _ INT
or V
DD _ EXT
or V
DD _ DDR 2
Valid 0 200 ms
t
CLKRST
CLKIN Valid Before RESET Deasserted 10
2
ms
t
PLLRST
PLL Control Setup Before RESET Deasserted 20
3
ms
Switching Characteristic
t
CORERST
Core Reset Deasserted After RESET Deasserted 4096 × t
CK
+ 2 × t
CCLK
4, 5
ms
1
Valid V
DD _ INT
assumes that the supply is fully ramped to its nominal value. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the
design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles.
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on t
SRST
specification in Table 19. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
Figure 6. Power-Up Sequencing
t
RSTVDD
t
CLKVDD
t
CLKRST
t
CORERST
t
PLLRST
V
DDEXT
V
DDINT
CLKIN
CLK_CFG1–0
RESET
RESETOUT
t
IVDDEVDD