Datasheet
Rev. 0 | Page 22 of 72 | June 2010
ADSP-21469
Figure 5. Core Clock and System Clock Relationship to CLKIN
LOOP
FILTER
CLKIN
PCLK
DDR2_CLK
DDR2
DIVIDER
B
YP
A
S
S
M
U
X
DIVIDE
BY 2
CCLK
BY
P
A
S
S
M
U
X
PLL
XTAL
CLKIN
DIVIDER
RESETOUT
RESET
BUF
VCO
BUF
PLLI
CLK
PLL
DIVIDER
CLK_CFGx/PMCTL (2xPLLM)
PIN MUX
RESETOUT
CLKOUT (TEST ONLY)
DELAY OF
4096 CLKIN
CYCLES
CORERST
CCLK
PCLK
CLK_CFGx/
PMCTL
LINK PORT
CLOCK
DIVIDER
LCLK
B
Y
P
A
S
S
M
U
X
PMCTL
(PLLBP)
PMCTL
(PLLBP)
PMCTL
(INDIV)
PMCTL
(LCLKR)
PMCTL
(DDR2CKR)
PMCTL
(PLLD)
PLL
MULTIPLIER
f
INPUT
f
CCLK