Datasheet

Rev. 0 | Page 10 of 72 | June 2010
ADSP-21469
Delay Line DMA
The ADSP-21469 processor provides delay line DMA function-
ality. This allows processor reads and writes to external delay
line buffers (and hence to external memory) with limited core
interaction.
Scatter/Gather DMA
The ADSP-21469 processor provides scatter/gather DMA func-
tionality. This allows processor DMA reads/writes to/from non-
contiguous memory blocks.
IIR Accelerator
The IIR (infinite impulse response) accelerator consists of a
1440 word coefficient memory for storage of biquad coeffi-
cients, a data memory for storing the intermediate data, and one
MAC unit. A controller manages the accelerator. The IIR accel-
erator runs at the peripheral clock frequency.
FFT Accelerator
FFT accelerator implements radix-2 complex/real input, com-
plex output FFT with no core intervention. The FFT accelerator
runs at the peripheral clock frequency.
FIR Accelerator
The FIR (finite impulse response) accelerator consists of a 1024
word coefficient memory, a 1024 word deep delay line for the
data, and four MAC units. A controller manages the accelerator.
The FIR accelerator runs at the peripheral clock frequency.
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues.
Program Booting
The internal memory of the ADSP-21469 boots at system
power-up from an 8-bit EPROM via the external port, link port,
an SPI master, or an SPI slave. Booting is determined by the
boot configuration (BOOTCFG2–0) pins in Table 8.
The Running Reset feature allows a user to perform a reset of
the processor core and peripherals, without resetting the PLL
and DDR2 DRAM controller or performing a Boot. The func-
tionality of the RESETOUT
pin also acts as the input for
initiating a Running Reset. For more information, see the
ADSP-214xx SHARC Processor Hardware Reference.
Power Supplies
The processors have separate power supply connections
for the internal (V
DD_INT
), external (V
DD_EXT
), and analog
(V
DD_A
) power supplies. The internal and analog supplies must
meet the V
DD_INT
specifications. The external supply must meet
the V
DD_EXT
specification. All external supply pins must be con-
nected to the same power supply.
Note that the analog supply pin (V
DD_A
) powers the processor’s
internal clock generator PLL. To produce a stable clock, it is rec-
ommended that PCB designs use an external filter circuit for the
V
DD_A
pin. Place the filter components as close as possible to
the V
DD_A
/AGND pins. For an example circuit, see Figure 3. (A
recommended ferrite chip is the muRata BLM18AG102SN1D).
To reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for V
DD_INT
and GND. Use wide
traces to connect the bypass capacitors to the analog power
(V
DD_A
) and ground (AGND) pins. Note that the V
DD_A
and
AGND pins specified in Figure 3 are inputs to the processor and
not the analog ground plane on the board—the AGND pin
should connect directly to digital ground (GND) at the chip.
Table 7. DMA Channels
Peripheral DMA Channels
SPORTs 16
IDP/PDAP 8
SPI 2
UART 2
External Port 2
Link Port 2
Accelerators 2
Memory-to-Memory 2
MLB
1
1
Automotive models only.
31
Table 8. Boot Mode Selection
BOOTCFG2–0 Booting Mode
000 SPI Slave Boot
001 SPI Master Boot
010 AMI Boot (for 8-bit Flash boot)
011 No boot occurs, processor executes from
internal ROM after reset
100 Link Port 0 Boot
101 Reserved
Figure 3. Analog Power (V
DD_A
) Filter Circuit
HI Z FERRITE
BEAD CHIP
LOCATE ALL COMPONENTS
CLOSE TO VDD_A AND AGND PINS
VDD_A
100nF 10nF 1nF
ADSP-2146x
V
DD_INT
AGND