Datasheet

Rev. D | Page 48 of 56 | April 2013
ADSP-21371/ADSP-21375
JTAG Test Access Port and Emulation
Table 41. JTAG Test Access Port and Emulation
Parameter Min Max Unit
Timing Requirements
t
TCK
TCK Period t
CK
ns
t
STAP
TDI, TMS Setup Before TCK High 5 ns
t
HTAP
TDI, TMS Hold After TCK High 6 ns
t
SSYS
1
System Inputs Setup Before TCK High 7 ns
t
HSYS
1
System Inputs Hold After TCK High 18 ns
t
TRSTW
TRST Pulse Width 4 × t
CK
ns
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 7 ns
t
DSYS
2
System Outputs Delay After TCK Low t
CK
2 + 7 ns
1
System Inputs = ADDR15–0, CLKCFG1–0, RESET, BOOT_CFG1–0, DAI_Px, and FLAG3–0.
2
System Outputs = DAI_Px, ADDR15–0, RD, WR, FLAG3–0, EMU, and ALE.
Figure 35. IEEE 1149.1 JTAG Test Access Port
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS