Datasheet

ADSP-21371/ADSP-21375
Rev. D | Page 47 of 56 | April 2013
TWI Controller Timing
Table 40 and Figure 34 provide timing information for the TWI
interface. Input signals (SCL, SDA) are routed to the
DPI_P14–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DPI_P14–1 pins.
Table 40. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices
1
Parameter
Standard Mode Fast Mode
Min Max Min Max Unit
f
SCL
SCL Clock Frequency 0 100 0 400 kHz
t
HDSTA
Hold Time (repeated) Start Condition. After This
Period, the First Clock Pulse is Generated. 4.0 0.6 μs
t
LOW
Low Period of the SCL Clock 4.7 1.3 μs
t
HIGH
High Period of the SCL Clock 4.0 0.6 μs
t
SUSTA
Setup Time for a Repeated Start Condition 4.7 0.6 μs
t
HDDAT
Data Hold Time for TWI-Bus Devices 0 0 μs
t
SUDAT
Data Setup Time 250 100 ns
t
SUSTO
Setup Time for Stop Condition 4.0 0.6 μs
t
BUF
Bus Free Time Between a Stop and Start Condition 4.7 1.3 μs
t
SP
Pulse Width of Spikes Suppressed By the Input Filter N/A N/A 0 50 ns
1
All values referred to V
IHmin
and V
ILmax
levels. For more information, see Electrical Characteristics on page 17.
Figure 34. Fast and Standard Mode Timing on the TWI Bus
PSS Sr
DPI_P14–1
SDA
DPI_P14–1
SCL
t
BUF
t
SUSTO
t
SP
t
SUSTA
t
HIGH
t
HDDAT
t
HDSTA
t
HDSTA
t
SUDAT
t
LOW