Datasheet

ADSP-21371/ADSP-21375
Rev. D | Page 45 of 56 | April 2013
SPI Interface—Slave
Table 38. SPI Interface Protocol—Slave Switching and Timing Specifications
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
SPICLKS
Serial Clock Cycle 4 × t
PCLK
– 2 4 × t
PCLK
– 2 ns
t
SPICHS
Serial Clock High Period 2 × t
PCLK
– 2 2 × t
PCLK
– 2 ns
t
SPICLS
Serial Clock Low Period 2 × t
PCLK
– 2 2 × t
PCLK
– 2 ns
t
SDSCO
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
2 × t
PCLK
2 × t
PCLK
2 × t
PCLK
2 × t
PCLK
ns
t
HDS
Last SPICLK Edge to SPIDS Not Asserted (CPHASE=0) 2 × t
PCLK
2 × t
PCLK
ns
t
SSPIDS
Data Input Valid to SPICLK edge (Data Input Set-up Time) 2 2 ns
t
HSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid 2 2 ns
t
SDPPW
SPIDS Deassertion Pulse Width (CPHASE=0) 2 × t
PCLK
2 × t
PCLK
ns
Switching Characteristics
t
DSOE
SPIDS Assertion to Data Out Active 0 6.8 0 6.8 ns
t
DSDHI
SPIDS Deassertion to Data High Impedance 0 9.9 0 6.8 ns
t
DDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 9.5 ns
t
HDSPIDS
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t
PCLK
2 × t
PCLK
ns
t
DSOV
SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t
PCLK
5 × t
PCLK
ns
Figure 32. SPI Slave Timing
t
SPICHS
t
SPICLS
t
SPICLKS
t
HDS
t
SDPPW
t
SDSCO
t
DSOE
t
DDSPIDS
t
DDSPIDS
t
DSDHI
t
HDSPIDS
t
HSPIDS
t
SSPIDS
t
DSDHI
t
DSOV
t
HSPIDS
t
HDSPIDS
SPIDS
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
CPHASE = 1
CPHASE = 0
SPICLK
(CP = 0,
CP = 1)
(INPUT)
t
SSPIDS