Datasheet

Rev. D | Page 44 of 56 | April 2013
ADSP-21371/ADSP-21375
SPI Interface—Master
The processor contains two SPI ports. Both primary and sec-
ondary are available through DPI only. The timing provided in
Table 37 and Table 38 applies to both.
Table 37. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid To SPICLK Edge (Data Input Setup Time) 8.2 ns
t
HSPIDM
SPICLK Last Sampling Edge To Data Input Not Valid 2 ns
Switching Characteristics
t
SPICLKM
Serial Clock Cycle 8 × t
PCLK
– 2 ns
t
SPICHM
Serial Clock High Period 4 × t
PCLK
– 2 ns
t
SPICLM
Serial Clock Low Period 4 × t
PCLK
– 2 ns
t
DDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time) 2.5 ns
t
HDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 4 × t
PCLK
– 2 ns
t
SDSCIM
DPI Pin (SPI Device Select) Low to First SPICLK Edge 4 × t
PCLK
– 2 ns
t
HDSM
Last SPICLK Edge to DPI Pin (SPI Device Select) High 4 × t
PCLK
– 2 ns
t
SPITDM
Sequential Transfer Delay 4 × t
PCLK
– 1 ns
Figure 31. SPI Master Timing
t
SPICHM
t
SDSCIM
t
SPICLM
t
SPICLKM
t
HDSM
t
SPITDM
t
DDSPIDM
t
HSPIDM
t
SSPIDM
DPI
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
CPHASE = 1
CPHASE = 0
t
HDSPIDM
t
HSPIDM
t
HSPIDM
t
SSPIDM
t
SSPIDM
t
DDSPIDM
t
HDSPIDM
SPICLK
(CP = 0,
CP = 1)
(OUTPUT)