Datasheet

ADSP-21371/ADSP-21375
Rev. D | Page 43 of 56 | April 2013
S/PDIF Receiver
For the ADSP-21371, the following section describes timing as it
relates to the S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × Frame Sync clock. The S/PDIF
receiver information does not apply to the ADSP-21375.
Table 36. S/PDIF Receiver Internal Digital PLL Mode Timing
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Switching Characteristics
t
DFSI
LRCLK Delay After Serial Clock 5 5 ns
t
HOFSI
LRCLK Hold After Serial Clock –2 –2 ns
t
DDTI
Transmit Data Delay After Serial Clock 5 5 ns
t
HDTI
Transmit Data Hold After Serial Clock –2 –2 ns
t
SCLKIW
1
Transmit Serial Clock Width 52 38.5 ns
1
Serial lock frequency is 64 × Frame Sync where FS = the frequency of LRCLK.
Figure 30. S/PDIF Receiver Internal Digital PLL Mode Timing
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
DRIVE EDGE
t
SCLKIW
t
DFSI
t
HOFSI
t
DDTI
t
HDTI