Datasheet

Rev. D | Page 42 of 56 | April 2013
ADSP-21371/ADSP-21375
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in Table 34. Input signals are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Oversampling Clock (HFCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This
HFCLK input is divided down to generate the biphase clock.
Table 34. S/PDIF Transmitter Input Data Timing
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
SISFS
1
Frame Sync Setup Before Serial Clock Rising Edge 3 3 ns
t
SIHRS
1
Frame Sync Hold After Serial Clock Rising Edge 3 3 ns
t
SISD
1
Data Setup Before Serial Clock Rising Edge 3.2 3 ns
t
SIHD
1
Data Hold After Serial Clock Rising Edge 3 3 ns
t
SITXCLKW
Transmit Clock Width 9 9 ns
t
SITXCLK
Transmit Clock Period 20 20 ns
t
SISCLKW
Clock Width 36 36 ns
t
SISCLK
Clock Period 80 80 ns
1
The data, serial clock, and frame sync can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either CLKIN
or any of the DAI pins.
Figure 29. S/PDIF Transmitter Input Timing
SAMPLE EDGE
DAI_P20–1
(TxCLK)
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
t
SITXCLKW
t
SITXCLK
t
SISCLKW
t
SISCLK
t
SISFS
t
SIHFS
t
SISD
t
SIHD
Table 35. Oversampling Clock HFxCLK) Switching Characteristics
Parameter Max Unit
HFCLK Frequency for HFCLK = 384 × Frame Sync Oversampling Ratio × Frame Sync <= 1/t
SITXCLK
MHz
HFCLK Frequency for HFCLK = 256 × Frame Sync 49.2 MHz
Frame Rate (FS) 192.0 kHz