Datasheet

ADSP-21371/ADSP-21375
Rev. D | Page 41 of 56 | April 2013
S/PDIF Transmitter
For the ADSP-21371, serial data input to the S/PDIF transmitter
can be formatted as left-justified, I
2
S, or right-justified with
word widths of 16-, 18-, 20-, or 24-bits. The following sections
provide timing for the transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 26 shows the right-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is delayed 12-bit clock peri-
ods (in 20-bit output mode) or 16-bit clock periods (in 16-bit
output mode) from an LRCLK transition, so that when there are
64 serial clock periods per LRCLK period, the LSB of the data
will be right-justified to the next LRCLK transition.
S/PDIF transmitter information does not apply to the
ADSP-21375.
Figure 27 shows the default I
2
S-justified mode. LRCLK is low
for the left channel and high for the right channel. Data is valid
on the rising edge of serial clock. The MSB is left-justified to an
LRCLK transition but with a single serial clock period delay.
Figure 28 shows the left-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is left-justified to an LRCLK
transition with no MSB delay.
Figure 26. Right-Justified Mode
Figure 27. I
2
S-Justified Mode
Figure 28. Left-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSB LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
t
RJD
MSB
LEFT/RIGHT CHANNEL
LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
t
I2SD
MSB
LEFT/RIGHT CHANNEL
LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
t
LJD