Datasheet

ADSP-21371/ADSP-21375
Rev. D | Page 39 of 56 | April 2013
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 32. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the PDAP, see the
PDAP chapter of the ADSP-2137x SHARC Processor Hardware
Reference.
Note that the 20-bits of external PDAP data can be provided
through the external port DATA31–12 pins. On the
ADSP-21375 processors, PDAP can not be multiplexed on the
external port (since only DATA15–0). Use the SRU DAI
instead.
Table 32. Parallel Data Acquisition Port (PDAP)
Parameter Min Max Unit
Timing Requirements
t
SPCLKEN
1
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2.5 ns
t
HPCLKEN
1
PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2.5 ns
t
PDSD
1
PDAP_DAT Setup Before Serial Clock PDAP_CLK Sample Edge 3.85 ns
t
PDHD
1
PDAP_DAT Hold After Serial Clock PDAP_CLK Sample Edge 2.5 ns
t
PDCLKW
Clock Width (t
PCLK
× 4) ÷ 2 – 3 ns
t
PDCLK
Clock Period t
PCLK
× 4 ns
Switching Characteristics
t
PDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t
PCLK
+ 3 ns
t
PDSTRIB
PDAP Strobe Pulse Width 2 × t
PCLK
– 1 ns
1
Data source pins are DATA31–12 or DAI pins. Source pins for serial clock and frame sync are: 1) DATA11–10 pins, 2) DAI pins.
Figure 24. PDAP Timing
DAI_P20–1
(PDAP_CLK)
SAMPLE EDGE
DAI_P20–1
(PDAP_HOLD)
DAI_P20–1
(PDAP_STROBE)
t
PDSTRB
t
PDHLDD
t
PDHD
t
PDSD
t
SPHOLD
t
HPHOLD
t
PDCLK
t
PDCLKW
DAI_P20–1/
ADDR23–4
(PDAP_DATA)